Flash Memory Summit 2017
At FMS 2017, Xilinx will be showcasing next-generation reconfigurable storage acceleration solutions. Join us at the show for a first-hand look and to connect with Xilinx technology experts.
During Exhibit Hours | Xilinx Booth
The following demos will be featured from Xilinx and its ecosystem throughout the show.
Xilinx Booth Demonstrations
The Xilinx single-chip storage solution integrates NVMe-over-Fabric and targets RDMA offloads with a processing subsystem to provide a very power-efficient and low-latency solution compared to existing products that require both an external host chip and a Network Interface Card (NIC). This 2x100 GE-based platform enables customers to implement value-added storage workload acceleration, such as compression and erasure code.
Programmable Controller for Multi-Source Flash
TrueFlash™ modular controller architecture from Burlywood accelerates time-to-market of new NAND adoption while delivering disruptive cost and performance benefits to cloud, all-flash-array, and hyper-converged OEM customers. Built on Xilinx UltraScale+™ FPGAs, Burlywood’s TrueFlash takes advantage of the power, performance, and cost improvements of Xilinx devices while allowing customers to quickly optimize solutions for both NAND and applications, and to qualify multiple NAND types using the same controller.
Computational Storage Subsystem (CSS) for I/O Acceleration
ScaleFlux Computational Storage Subsystem (CSS) uniquely solves both compute and storage I/O bottlenecks. OpenZFS supports on-the-fly compression of all user data, but dramatically reduces performance due to additional CPU overhead. CSS compression accelerates throughput an order-of-magnitude without the costly CPU overhead, resulting in an optimal balance of performance and capacity.
Xilinx Ecosystem Demonstrations on FMS Show Floor
Everspin Technologies: Booth #319
Demonstration of Everspin Technology nvNITRO™ SSD products showcasing a combination of Everspin ST-MRAMs and Xilinx FPGAs. Coupling ST-MRAM to a highly optimized NVMe controller with extended byte mode capabilities significantly reduces latency and simplifies the protection of mission-critical data.
IntelliProp, Inc.: Booth #821
Demonstrations include IntelliProp’s Gen-Z Hybrid Memory Controller based on a Zynq® UltraScale+ MPSoC and IntelliProp’s production ready NVMe Host Accelerator IP core on a Zynq UltraScale+ device and the IntelliProp NVMe Hybrid Memory Controller based on a Kintex® UltraScale™ FPGA.
IP-Maker: Booth #717
Demonstration shows the benefits of an ultra-low latency NVMe-based storage drive in a database application (SQL server, OLTP profile). The performance (transactions per minute) is increased thanks to the sub-microsecond NVMe management latency, executed by the full hardware IP-Maker NVMe IP in the Xilinx Virtex®-7 FPGA.
Kazan: Booth #702
Demonstrations based on the Xilinx Virtex UltraScale VU095 FPGA will showcase the capabilities of an NVMe over Fabrics™ bridge. These solutions enable highly scalable pools of NVMe SSDs to be accessed and shared across an Ethernet fabric, enabling drastically higher levels of storage utilization and forming the basis of the next-generation datacenter architecture.
Mobiveil: Booth #610
Demonstration showcasing Mobiveil’s FPGA-based LDPC Encoder / Decoder flash reliability solution delivering industry-leading flash endurance and retention through advanced LDPC error correction coupled with statistical digital signal processing (S-DSP) at the lowest power and smallest foot print.
PLDA: Booth #826
Demonstration of a many-channel DMA for virtualized PCIe systems, vDMA IP. The demo consists of a SR-IOV enabled server platform hosting three virtual machines, each generating DMA traffic over a PCIe 3.0 connection to a Xilinx Kintex UltraScale endpoint board. Each VM is assigned two VF attached to 32 DMA channels (totaling 192 channels), generating simultaneous bidirectional traffic on every channel.
Smart IOPS: Booth #609
Demo features Smart IOPS Data Engine SSDs running on a Kintex UltraScale FPGA that pushes the limits of PCIe Gen 3.0 throughput and sustains 1.7 million IOPS.
Xilinx Booth #126
Santa Clara Convention Center
Santa Clara, CA
Tuesday, August 8
4:00 PM – 7:00 PM
Wednesday, August 9
12:00 PM – 7:00 PM
Thursday, August 10
10:00 AM – 2:30 PM
Xilinx Conference Participation
Xilinx experts will be participating in the following product showcases.
Thursday, August 10 | 10:15 AM – 10:30 AM
Reconfigurable Storage Acceleration for Next Generation NVMe Platforms
FMS Theater Presentation
Presenter: Rakesh Cheerla
Thursday, August 10 | 1:30 PM – 2:45 PM
Accelerating Data Analytics Using FPGAs and an Integrated Flash Storage Solution
The advent of big data has led to tremendous compute requirements for real-time analytics. Both centralized and distributed solutions often fall short in performance, and meanwhile the amount of data keeps growing. One solution is to offload compute to a field customizable hardware implementation with an integrated flash storage solution. This approach can provide 10-25x acceleration over other methods. The cost and complexity are both reasonable, and leading FPGA manufacturers to offer tools, platforms, and libraries to implement accelerator workloads on FPGAs. These are used in popular database software such as RDBMS PostgreSQL or other NoSQL, and columnar storage based databases. Data Analytics, done on FPGA, integrates SQL and other database operational engines with the flash storage to provide significant improvement over pure software based solutions. The result can be a significant reduction in operating costs (OPEX) for datacenters focused on data analysis.
Presenter : HK Verma, Principal Engineer, Xilinx
Thursday, August 10 | 1:30 PM – 4:15 PM
Using FPGAs to Accelerate NVMeoF-Based Storage Networks
NVMe over Fabrics (NVMeoF) allows designers to network large numbers of NVMe-based storage arrays. Though this approach addresses the capacity scaling, resulting data transfers are CPU intensive and hence can bog down the entire solution. A promising approach is to use hardware accelerators to offload the protocols for both NVMe-over-fabrics and RDMA. An even better solution goes beyond the protocols and adds custom and reconfigurable accelerators in the data path. This approach eliminates the CPU bottleneck entirely. Example accelerators utilize FPGAs to achieve significant acceleration while giving a total solution cost advantage to the end customer.
Presenter: Deboleena Minz Sakalley, Senior Staff Design Engineer, Xilinx