The Block Memory Generator LogiCORE™ IP (Block Mem Gen) replaces the following two legacy CORE Generator™ LogiCOREs:

• Dual Port Block Memory (v6.x)
• Single Port Block Memory (v6.x)

v2.4 of this kit has been updated to support migration of these cores to all released versions of Block Memory Generator up to v2.4.

Cores generated by the Block Memory Generator customizer are not drop-in replacements for the v6.x cores above as there are a number of feature and interface changes in the Block Memory Generator.

To help you migrate designs containing legacy v6.x Dual and Single Port Block Memory LogiCOREs to the new Block Memory Generator core, Xilinx provides the Block Memory Generator Migration Kit to take care of all your migration-related tasks without the need to manually edit your design.

The Migration Kit includes the following components:

• A Migration Guide documenting manual and automated migration methods, as well as a review of the feature differences
  
  
• PERL scripts to automate migration
  • Migration script ("bmg_migrate.pl") to convert v6.x block memory HDL instances and netlists in your design
  • XCO recovery script ("recover_xco.pl") to recover XCO and COE configuration files from v6.x core netlists

Why Migrate your Design?

• Migrating v6.x CORE Generator block memory blocks in your design to Block Memory Generator style cores allows you to port existing designs to new Xilinx architectures.
  
  
• Design conversion also allows you to take advantage of the
  new feature enhancements available in this core today, as well as any enhancements and bug fixes which will be made available to it in the future.
  
  
• No further enhancements are being made to the v6.x Dual Port and Single Port Block Memory LogiCOREs.
  
  

• Regardless of whether you convert your designs manually or via automated means using this Migration Kit, it is highly recommended that you first evaluate the differences between the old and new cores before starting the migration process.
  
  
• The Migration Kit is provided as a tactical utility under the terms of the Reference Design License. You will be asked to accept this license when downloading the kit.

• Download the Block Memory Generator Migration Kit* archive (requires a Xilinx.com login).
• If you have problems downloading the kit from the link on this page, please access it from the Application Notes area as follows:
  • From any page on Xilinx.com, click the Documentation link at the very top of the page and navigate as follows:
    
    Documentation-> Application Notes-> Memory Interface & Storage Element-> RAM & ROM
    
    
  • Select the xapp917.zip file in the XAPP917 near the bottom to access the kit.
    
    
• Extract the archive to a temporary directory.
  
  
• Read the Block Memory Generator Migration Guide* for detailed use instructions.
• View the appropriate Block Memory Generator Release Note* for information on known issues.

  * Refer to the right sidebar at the top of this page to access the kit and migration documentation.

• The latest version of the kit now supports retargeting to all released versions of the Block Memory Generator core.