Xilinx supports Full System Hardware Evaluation of the 3GPP LTE Turbo Decoder and Encoder LogiCORE™ IP cores.

The evaluation license keys for these cores will enable you to parameterize, generate and instantiate this IP in your design. They will also allow you to perform functional and timing simulation, generate a bitstream, and download and configure your design in hardware. The resulting IP will be fully functional in the FPGA for 2-3 hours, after which it will cease to function. To restore the evaluation core's operation in your design, simply reconfigure the FPGA with the bitstream.

To perform a Full System Hardware Evaluation:

1. Make sure you have satisfied the requirements.
2. (Decoder core only:
• Register to request access to the 3GPP LTE Decoder Evaluation Core. Xilinx IP Marketing will review your request.
• Upon approval, log into the 3GPP LTE Turbo Decoder Evaluation Member Lounge
3. Generate and install a Full System Hardware Evaluation License Key for the core:.

• 3GPP LTE Turbo Encoder
• 3GPP LTE Turbo Decoder (approved users only)
  
  
4. Follow the general instructions below on Generating the Core.
5. To perform an in-depth evaluation in hardware in your own design:
• Instantiate the core in your own design, place and route the design using the ISE® software, then generate a bitstream and use it to program an appropriate FPGA device.

• Start the CORE Generator™ software using either of the following methods:
  • From ISE: Select Projects -> New Source -> IP (CORE Generator and Architecture Wizard)
  • From Windows: Select All Programs -> Xilinx 10.1 Design Suite -> ISE -> Accessories -> CORE Generator
• The 3GPP LTE Turbo cores are located in the Communication and Networking folder in the IP catalog section of the CORE Generator window, under the Error Correction subfolder.

You can learn more about the 3GPP LTE Turbo Decoder and 3GPP LTE Turbo Encoder products by visiting the product pages.

Purchase this Xilinx LogiCORE IP product from your local Xilinx Sales Representative.