Xilinx offers a Full System Hardware Evaluation for all LogiCORE™ IP Initiator/Target for PCI™ and PCI-X™ cores. For the 32-bit Initiator Target cores, the evaluation is available any time using the instructions below. For an evaluation of any other Initiator/Target core, contact your local FAE.

The 3-month license key allows you to parameterize, generate and instantiate this IP in your design. You will also be able to perform functional and timing simulation as well as create a bitstream, and download and configure your design in hardware. The IP will be fully functional for approximately 9 hours at 66 MHz and 4 hours at 33 MHz, after which it will "time out" and you will need to download and configure the FPGA again.

• Download and Install ISE® 10.1 or later revision Service Pack along with the most recent IP Update.
• Request an evaluation license:
  • For the 32-bit Initiator/Target cores, complete this form to generate a license.
  • For all other cores, contact your local FAE.
• You will receive an email with a license attached. Install the license as directed in the email you received.
• Start up CORE Generator™ software.
• To access the core, double-click on the "Standard Bus Interfaces" folder in the left panel of the CORE Generator software GUI, then double-click on the "PCI" folder.
• Double-click the appropriate core name.
• Select the desired options, then click "Generate."
• The following support files: .veo, .vho, .xco, .xcp, and <core_name>_flist.txt, a subdirectory named <core_name>, and a README file, readme_<core_name>.txt, with additional details, are generated.
• Refer to the Getting Started guide found in the <core_name>/docs directory for instructions on running the demonstration implementation script.

Ordering Information

Learn more about the Initiator/Target for PCI/PCI-X cores.

You can purchase this Xilinx LogiCORE IP from your local Xilinx sales representative.