This page contains information on how to evaluate the various soft Tri-Mode Ethernet MAC cores delivered in ISE™ CORE Generator™ and EDK™.

While the soft TEMAC cores require purchase of a separate license, the HDL Wrappers and cores supporting the hard TEMAC blocks embedded in the fabric of Virtex™-4 FX and Virtex-5 LXT/SXT devices are delivered with full access in ISE or EDK at no additional cost.

A full listing of Xilinx TEMAC LogiCORE™ IP Offerings can be found in the TEMAC Product Offerings and System Requirements Schedule.

Standalone soft Tri-Mode Ethernet MAC (ISE CORE Generator)

Xilinx provides two ways to evaluate the standalone soft Tri-Mode Ethernet MAC (TEMAC) Core: Simulation Only and Full System Hardware Evaluation.

• Simulation Only Evaluation allows you to customize the core through a CORE Generator customization GUI and generate a SimPrim-based gate level model for functional simulation.
• A Full System Hardware Evaluation version of the TEMAC core allows you to do everything you can do with the fully licensed IP core, including configure place and route, simulate, estimate timing and program a Xilinx FPGA device.

XPS_LL_TEMAC (EDK)

• Xilinx supports Full System Hardware Evaluation of the soft TEMAC configuration of the XPS_LL_TEMAC core in EDK.

1. Make sure you have installed the required ISE software as specified in the requirements section above to ensure that you have the required software and IP core version. The Simulation Evaluation license key is shipped with the core by default.
2. Follow the general instructions below on Generating the Core.
3. Integrate the core into your design and perform a functional simulation. See the Getting Started Guide for more details.

XPS_LL_TEMAC (soft TEMAC configuration)

1. Make sure you have satisfied the requirements.
2. Follow the instructions on the Processor IP Evaluation page to perform a Full System Hardware Evaluation of the soft TEMAC configuration of the XPS_LL_TEMAC core.

Standalone soft TEMAC core

1. Make sure you have satisfied the requirements.
2. Generate a Full System Hardware Evaluation License Key.
   • The key will be generated and emailed to you automatically. Install the license as directed by the email instructions.
3. Follow the general instructions below on Generating the Core.
4. To familiarize yourself with the ISE design flow,
• Process the Example Design delivered with the core through ISE following the Quick Start instructions in the Getting Started Guide .
5. To perform an in-depth evaluation in hardware in your own design:
• Instantiate the core in your own design, place and route the design using ISE, then generate a bitstream and use it to program an appropriate FPGA device.

• Start the CORE Generator using either of the following methods:
  • From ISE: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
  • From Windows: Select Programs -> Xilinx -> Accessories -> CORE Generator
• The soft Tri-Mode Ethernet MAC core is located in the Communication and Networking folder in the IP catalog section of the CORE Generator window.

Refer to the Example Design Quick Start chapter of the Getting Started Guide for more detailed instructions on evaluating the core.

Please refer to Xilinx Answer # 25222 for the latest version of the Release notes for this core.