BINACHIP
Meet the performance and time-to-market constraints.
Use BINACHIP-FPGA to speed-up your PowerPC® based application on a Virtex™-II Pro platform FPGA. Whether you are using C/C++, MATLAB®, Assembly, or a combination thereof to develop your embedded application, the tool can take the existing binary executable and generate a new executable as well as custom hardware for acceleration on an FPGA platform. It also generates all the necessary hardware/software interfaces. This allows embedded application developers to leverage all of the features of the Virtex FPGA platform, without intrinsic knowledge of hardware design or the need to learn a new source language.
Below are more facts about BINACHIP:
Technology Brief
Overview of the technology
- BINACHIP technology enables the embedded application developer to meet their cost, area, performance and time-to-market constraints
- Starting with the binary or compiled executable of an embedded application BINACHIP-FPGA is able to perform hardware/software partitioning and create a new executable and FPGA hardware to improve the performance of the application by 10X – 50X
- No knowledge of the application, hardware design or the source code of the application is required
- BINACHIP-FPGA can also be used to translate entire embedded applications to FPGA implementations thus eliminating the processor or custom DSP
- For more information on the technology visit www.binachip.com
History of the company and origins of the technology
- Company was originally founded in 2003 and began operations and shipping product in 2006
- BINACHIP’S core technology is the result of work done at Northwestern University. The Northwestern team developed the FREEDOM compiler that takes digital signal processing (DSP) applications written in the assembly language and automatically generates VHDL or Verilog RTL code for commercial FPGAs
- Patent applied for in 2004 by Northwestern University, BINACHIP holds an exclusive license for the technology
- At BINACHIP this technology was extended to support multiple processors and FPGA architectures as well as hardware/software co-design
Language Backgrounder
Which languages are supported?
- Since BINACHIP tools work from the binary of an embedded application compiled for a specific target platform all source languages including C/C++, MATLAB, JAVA, Assembly are supported
- No software language subsets enforced
- No software coding styles enforced
How is parallelization achieved?
- Parallelism is achieved by loop unrolling
- Fine-grain parallelism using data scheduling techniques
- User can make area/performance trade-offs by controlling the amount of parallelism
Are multiple clock domains supported?
- At this point the tool supports a single clock domain. Support for multiple clock domains will be added in the future
Level of Abstraction - How different is it from coding in HDL?
- BINACHIP works from the binary of the embedded application and does not require any HDL coding
- Generates synthesizable Verilog or VHDL and a bit-true testbench for verification
- Source code does not need to be rewritten for synthesis
Is floating point operation supported?
- Floating point operations are supported through library calls to fixed point instructions and compiling the fixed point instructions to RTL
Is an interface to Matlab supported?
- Yes, application binaries developed in any/all source languages are supported
Are standalone function libraries available?
- Any standalone function library available in PowerPC, TI C6200 and ARM7™ binary can be compiled into RTL
What format is the synthesis output?
- BINACHIP-FPGA generates RTL code in standard Verilog and/or VHDL
- RTL is synthesizable and has been validated with Synplicity, and Xilinx synthesis tools
Quality of results / Optimization scenarios
- Speed-up of 10X – 50X can be achieved over a pure software implementation depending on the application
- User controlled or automated hardware/software co-design allows for area/performance trade-offs
- Supports advanced scheduling optimizations
Simulation and debugging flows
- BINACHIP-FPGA generates a bit-true simulation testbench to verify the functionality of the hardware/software co-design relative to the pure software implementation
- Testbenches have been fully tested and validated in the Xilinx/ModelSim and Synplicity/ModelSim flows
What is the learning curve?
- Easy-to-use Windows based graphical user interface
- Targeted towards embedded application developers rather than hardware designers
- No FPGA design knowledge necessary
- New users can ramp up in 1-2 days using the tutorials and training material provided
Skill pre-requisite
- Basic familiarity with software design tools is recommended
- Knowledge of hardware design tools is useful but not essential
Suitability and Fit
Who is the target audience?
- Embedded application developers targeting FPGA platforms
- Compute intensive applications unable to meet performance goals with a pure software implementation
Which applications segments are targeted by this product?
- Video CODEC applications such as H.264, MPEG4
- Security applications such as Encryption/Decryption
- Communication applications such as Viterbi encoding and decoding
- Any other compute intensive application that needs performance improvement
What are the characteristics of the target application?
- Embedded application running on an FPGA platform
- Compute intensive applications that need performance improvement
- Legacy applications that need to be migrated to a faster platform without source code changes
Main value proposition?
- Faster time-to-market by improving productivity and reducing the design time
- Reduced cost by going from multiple custom DSP’s to FPGAs
- Improved performance using a hardware/software co-design implementation
How can you find out if your application is a good candidate for this tool methodology?
- Compute intensive application with complex DSP algorithms
- Unable to meet performance requirement on existing hardware platform
- Embedded applications targeted towards a hardware/software co-design implementation
Language and methodology limitations
- No language or methodology limitations
Successful deployment examples
Customer testimonials
Pricing
Xilinx Integration
Which Xilinx devices/architectures are supported?
- Virtex-4
- Virtex-II Pro
- Spartan™-II
- Spartan-IIE
- Spartan-3/3E
- CoolRunner™-II
Which Xilinx CPUs are supported?
- PowerPC
- MicroBlaze™ support available with consulting services
- PicoBlaze™ support available with consulting services
- Contact us at info@binachip.com to discuss CPU support
Is the Virtex-4 FX APU supported?
- Virtex-4 FX APU support available with consulting services
Inference of Xilinx Library components
- Built-in support for Xilinx architectures and library components
Benchmark studies targeting Xilinx
Flow integration with EDK/XPS, ISE™ Software, System Generator (Implementation)
- Fully tested and validated implementation flow with EDK/XPS, ISE software, System Generator
- For Xilinx design flow example visit www.binachip.com
Flow integration with EDK/XPS, ISE Software, System Generator (Simulation)
- Fully tested and validated simulation flow with EDK/XPS, ISE software, System Generator
- For Xilinx design flow example visit www.binachip.com
Getting Started
How to get started
- Xilinx ESL starter kit with a Virtex-II Pro development board available for $4,995 and up
- Contact sales@binachip.com for more information or to purchase starter kit
Design examples for various Xilinx boards
- Starter kit comes with a design example for a Virtex-II Pro development board and tutorial
Sales kits available?
(i.e. bundling of boards, software, examples for an integration out of the box experience)
- Xilinx ESL starter kit is available for purchase immediately
- Contact sales@binachip.com for more information or to purchase starter kit
Design services/ consultancy available?
- Yes, design and consulting services are available for Embedded application design, FPGA design and implementation as well as SoC design
- For more information visit www.binachip.com or email sales@binachip.com
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