イーサネット 1000BASE-X PCS/PMA または SGMII

The Ethernet 1000BASE-X PCS/PMA core is designed to the IEEE 802.3-2002 specification. Features include:

• Full Duplex operation
• The core is parameterized through the CORE Generator™, allowing you to tailor the core to your specific feature set requirements
• Option to implement CRC logic in the Virtex™-5 LXT, Virtex-4 FX, and Virtex-II Pro RocketIO™ Multi-Gigabit Transceiver
• Optional MDIO interface, or simplified interface with configuration vector

• A 1000BASE-X PCS with a Ten Bit Interface (TBI) for connection to industry standard SerDes devices, or
• An integrated 1000BASE-X PCS/PMA, which allows you to simplify your board design.
• SGMII to support multiple data rates

In all of the above cases the front end interface is GMII, which may be either internal to the FPGA, or implemented as an external interface using the FPGA package pins.

• Bridging applications - applications requiring the transfer of Ethernet frames across a medium different from Ethernet, where protocol termination is not required (Examples: GFP-T mapping, switch port interfaces).
• Porting third party Ethernet MACs to Virtex-5 LXT, Virtex-4 FX, Virtex-II Pro MGT PCS/PMA.
• Interfacing Ethernet to other standard interfaces (e.g., SPI-4.2).
• Backplane applications requiring 1 Gbps data rates
• Chip-chip or board-board 1 Gbps interfaces

This GMII to 1000BASE-X PCS/PMA function was first released as an integrated interface option of the Xilinx Gigabit Ethernet MAC LogiCORE solution (v2.1). It is now available as a standalone core offered at no additional charge to all Xilinx ISE customers. An evaluation version is delivered in standard ISE releases and selected IP Updates for the CORE Generator. This default "simulation-only" evaluation version allows you to integrate the core into your design and perform functional verification and timing analysis. To generate a bitstream for designs containing this core, you must additionally register for this core, request a full access electronic license key, and install the key on your host machine.

Registration and licensing information, as well as instructions for downloading the core can be found in the Register link on the left side at the top of this page.

The pinouts for all configurations of the core are flexible for the most part.

The main constraints on the PCS/PMA sections of the pinouts are the general guidelines related to the MGTs and DCMs in the Virtex-II Pro™ architecture as described in detail in the RocketIO User Guide.

For the GMII and TBI pinouts, the only constraints are the general guidelines related to I/O Banking in your target FPGA architecture. In addition, it is also recommended that IO's associated with a specific clock domain be grouped together in a separate I/O bank.

Yes. The following features may be omitted when customizing the core via the CORE Generator software:

• Auto-Negotiation per Clause 37 of IEEE 802.3-2002
• Management interface (MDIO)
• Transmitter Elastic Buffer
• 1000BASE-X PCS with TBI or PMA

Please refer to 1000BASE-X PCS/PMA or SGMII datasheet for detailed device utilization.

Stratos Lightwave RJK-ST11 and R14K-ST11 Optical Transceivers have been tested with the 1000BASE-X PCS/PMA configuration of the Gigabit Ethernet MAC.

The core has been designed to be compatible with industry standard GE PHYs with GMII interfaces and 1000BASE-X compatible optical modules. Please contact your Xilinx FAE for more details on the latest interoperability testing status.

To try out the customization GUI and generate a gate level SimPrim library model which you can use to functionally evaluate the core in your system ("Simulation-only Evaluation"), follow the instructions regarding Xilinx ISE software requirements, Service Pack levels and IP Update installation requirements described on the Evaluation page.

If you additionally wish to perform a Full System Evaluation in hardware, you will also need to request a Full System Evaluation license from the Ethernet 1000BASE-X evaluation page in the Xilinx IP Evaluation Lounge.

See the  IP Release Notes for known issues, new features and patches

• [back to top]

The core is part of the Xilinx Platform FPGA SystemIO solution, which addresses all aspects of system connectivity in high-performance designs. Xilinx provides the most comprehensive gigabit Ethernet MAC offerings in the programmable industry. In addition to the Ethernet 1000BASE-X PCS/PMA core, Xilinx also provides:

• a 10/100 Ethernet MAC core with OPB interface for embedded MicroBlaze™ and PowerPC solutions,
• a 1 Gb Ethernet MAC with a choice of GMII interface, 1000BASE-X PCS with TBI, or integrated 1000BASE-X PCS/PMA, plus a configuration with a Processor Local Bus (PLB) interface
• a 10 Gb Ethernet MAC core
• a standalone XAUI core
• Tri-Mode Ethernet MAC core

View a complete listing of Xilinx Ethernet IP solutions for more details.