I2C Master/Slave Bus Controller (I2C-HS)

サポートするデバイス

• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-5 TXT
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX

The I2C-HS core implements a serial interface that meets the Philips I2C Bus® specification version 2.1. It is compliant with the PVCI (Peripheral Virtual Component Interface) standard which is an open standard for SoC On-Chip Bus. The I2C-HS is a microcode-free design developed for reuse in ASIC and FPGA imple-mentations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.

主要機能

• Compliant to version 2.1 of the I2C Bus standard
• The I2C Bus uses two wires to transfer information between devices connected to the bus: SCL (serial clock line) and SDA (serial data line)
• Data transfers up to 100 Kbps in standard mode, up to 400 Kbps in fast-mode, and up to 3.4 Mbps in high-speed mode