The core is compliant with clause 36 of the IEEE802.3 standard and implements 8B/10B coding, link synchronization, frame encapsulation generation / termination. The core also supports Auto-Negotiation (clause 37 of IEEE802.3 standard). In addition to standard compliance, the core provides support for proprietary or industry standard 2500Base-X 2.5Gbps, 2000Base-X 2Gbps ethernet connections.
主要機能
- Implements a 20-Bit SERDES interface and optionally, a 10-Bit DDR (Dual Data Rate) SERDES interface
- Extended 16-Bit GMII interface compatible with MorethanIP AnySpeed MAC Core
- Dual gigabit / 2.5Gbps implementation with embedded Virtex 5LXT SERDES or discrete SERDES solution
- Implements user controllable 1000Base-X Auto-Negotiation (IEEE 802.3 clause 37) which fully programmable node ability register
- Extended clause 45 MDIO slave PHY management interface which provides a standard interface for core configuration and management
