製品の詳細
資料
サポートするデバイス
- Spartan-3A
- Spartan-IIE
- Spartan-3
- Virtex
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-E
- Virtex-II
- Virtex-II Pro
The OPB IPIF/ V3 PCI Core Bridge design bridges the OPB IPIF (On-Chip Peripheral Bus Intellectual Property Interface) and the PCI64 Interface v3.0 core providing full bridge functionality between the Xilinx 32-bit OPB and a 32-bit V2.2 compliant PCI (Peripheral Component Interconnect) bus. Only 33/66 MHz, 32-bit PCI buses are supported at this time. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
主要機能
- One of the infrastructure cores supported by the Embedded Development Kit (EDK)
- 33/66 MHz, 32-bit PCI buses
- Utilizes the SRAM interface of the OPB IPIF for PCI data transfers
- OPB and PCI clocks are required to be a global buffer
