製品の詳細
サポートするデバイス
- Spartan-3
- Spartan-3A
- Spartan-3A DSP
- Spartan-3E
- Spartan-IIE
- Virtex
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
- Virtex-II
- Virtex-II Pro
システム要件
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception. Compatible with many common standards such as DVB, 3GPP2, IEEE802.16, HiperLAN, Intelsat IESS-308/309, the Viterbi Decoder LogiCORE™ IP, along with other forward error correction cores from Xilinx offers highly-flexible concatenated codecs. The Viterbi Decoder LogiCORE IP consists of two basic architectures: a fully parallel implementation which gives fast data throughput and a serial implementation which occupies a small area. The core also has a puncturing option, giving a large range of transmission rates and reducing the bandwidth requirement on the channel. Puncturing can also be carried out externally to the decoder and the erasure pins in the erasure bus ERASE can be asserted to indicate the presence of null-symbols.
主要機能
- Compatible with many common standards such as DVB ETS, 3GPP2, IEEE802.16, HiperLAN, and Intelsat IESS-308/309
- Parameterizable constraint length, convolution codes, traceback length and width for soft decision
- Decoder rates from 1/2 to 1/7 with erasure input for puncturing
- Provides a serial architecture for area optimization and a parallel architecture for speed optimization
- Supports a multi-channel mode that enables the decoding of up to 32 interlaced channels with a single Viterbi core
- Dual rate decoder, trellis mode, BER monitor, normalization, synchronization and best state options also available
- Any traceback length
