Advanced I/O Technology

Enabling Multiple System Integration

The CoolRunner™-II advanced I/O interface capability fully addresses all aspects of system connectivity in a wide range of product applications. This solution consists of both the physical interface and the protocols to maximize system interface bandwidth. CoolRunner-II CPLDs provide the fastest and most flexible electrical interface available on a consumer CPLD today.

Multiple I/O Banks

CoolRunner-II CPLDs feature multiple I/O banks, enabling easy communication between two distinct signal level interfaces such as different bus interface I/O voltage levels. This can also include voltage translation of peripheral devices and memory to microcontrollers, or communication between wired interfaces.
 

Figure 1

Multiple system integration is now available with CoolRunner-II CPLDs!

500 mV Input Hysteresis

Input hysteresis provides designers with a tool to minimize external components. Whether using the inputs to create a clock, or reducing the need for external buffers to sharpen up an input signal, CoolRunner-II CPLD inputs provide designers with a flexible and powerful features:

• Improved noise immunity
• Reduced power consumption
• Superior signal intergrity

Figure 2

Hysteresis (Schmitt trigger) input.

DataGATE

Greater low power designs can be attained with the use of Xilinx CoolRunner-II DataGATE technology. DataGATE disables unused input pins, reducing power consumption - almost 99% lower than traditional low power CPLDs! In all, DataGATE enables CoolRunner-II to be a small fraction of the system power consumption -- no other CPLD has this capability.

DataGATE permits:

• Input signal blocking
• Stops input switching
• No external devices
• Reduces power

Learn more information about the power reducing capabilities of DataGATE.

Support for Multiple I/O Standards

You can easily create standard chip-to-chip and chip-to-memory interfaces and thus remove discrete interface devices from your system. This saves you money and increases your system reliability.

• LVTTL and LVCMOS for standard chip-to-chip interfacing
• SSTL and HSTL for standard chip-to-memory interfacing

I/O Performance and Flexibility
	XC2C32A	XC2C64A	XC2C128	XC2C256	XC2C384	XC2C512
I/O Banks	2	2	2	2	4	4
LVTTL/ LVCMOS*
SSTL/ HSTL
Input Hysteresis Option
DataGATE
Bus Hold Output

Table 1

*1.5V inputs need hysteresis.

Additional Features

• Bus Hold Output keeps outputs in their in their last stable state for additional power reduction
• Up to four independent I/O banks make it easy to use different I/O standards in the same design.