The risk of deploying ASIC solutions has worsened in magnitude with the move to smaller process geometries. As design complexity increases, customers are looking for a viable solution that offers low design, unit, and total costs, high-level system integration, design flexibility, easy-to-use design tools, a rich selection of IP, and fastest time to market.

: Customers are increasingly turning to other alternatives to avoid the pitfalls of ASICs – high NRE and re-spin expenses, slow turnaround times, complex design environments, and hidden conversion, verification, and development costs. In this article, we’ll analyze two such alternatives: Xilinx® EasyPath™ FPGAs and structured ASICs.

Structured ASIC product offerings tend to be similar to FPGAs in that they have predefined combinations of gates, memory, and I/Os. However, their architectures tend to trade off flexibility in favor of reduced area to achieve their cost targets. The reality remains that a vast majority of designs intended for ASICs are originally prototyped in an FPGA, yet there are still problems with FPGA-to-structured-ASIC conversions. EasyPath FPGAs offer the best migration path to high-volume production at the lowest cost possible.

EasyPath FPGAs
EasyPath FPGAs are the industry’s only customer-specific and flexible solution for volume production priced lower than structured ASICs.

EasyPath FPGAs are identical to our standard FPGA offerings but use patented testing techniques and customer-specific test patterns to significantly improve FPGA yields. You can reap the benefits of these improved yields in the form of lower costs, because Xilinx only tests those parts of an FPGA that are actually used in your design.

L With EasyPath FPGAs, you can realize a 30-80% reduction in prices when you move to high volume, as compared to standard FPGAs. EasyPath FPGAs are available across six platforms, four different product families, and 28 different devices over a range of gate and memory counts.

EasyPath FPGAs are identical to their standard FPGA counterparts, effectively eliminating any conversion work. Once you have frozen your design, Xilinx can deliver EasyPath parts in high volume in eight weeks. This compares favorably against structured ASIC companies, which typically take 12-14 weeks from prototype signoff to production.

Structured ASICs
Structured ASICs are a variant of the gate arrays of yesteryear, but they use a “sea of modules” approach as opposed to a “sea of gates” approach. The architecture of each module varies depending on the vendor, but in general is some combination of NAND gates, inverters, flip-flops, and muxes.

Structured ASICs promise cost savings primarily as a result of customizing fewer mask layers per design, unlike standard cell ASICs that use all-custom metal layers. Structured ASICs use only the top few (typically two to four) metal layers; the base modules are all buried in the lower layers, with their ports coming up to the programmable layers. During the fabrication phase, the connections between various ports are made to realize the requisite logic.

The Lowest Total Cost Solution
Figure 1 shows the comparative economics of standard cell ASICs, structured ASICs, FPGAs, and EasyPath FPGAs. FPGAs have traditionally offered a zero-NRE solution, which has led to their broad adoption. Standard cell ASICs have a high NRE and a relatively low unit cost, but with the overhead discussed earlier. Structured ASICs promise to lower the NRE at a unit cost that is higher than that of standard cell ASICs, but lower than that of standard FPGAs.

With next-generation EasyPath FPGAs, you can now enjoy unit prices as well as NREs that are lower than structured ASICs. The combination of the industry’s lowest NRE charges (starting at $75K); low cost design tools and IP; prices below structured ASICs; fastest times to production; and no hidden conversion charges show how EasyPath FPGAs are the industry’s lowest total cost solution for volume production.

Unmatched Choice of Platforms
Structured ASIC vendors can roughly be grouped into two camps based on their ability to address IP-centric designs. On the one hand are those that have a wide portfolio of IP; on the other are companies that typically can only address generic designs. With the recent announcement of next-generation EasyPath FPGAs from Xilinx, both of these segments can be addressed economically and efficiently.

Xilinx now offers four families and six platforms, with 28 devices from which to choose. This comes with all the benefits of the FPGA ecosystem that Xilinx customers are already used to – hard IP such as the IBM™ PowerPC™, MGTs, and XtremeDSP™ blocks, as well as 600+ proven soft IP cores and low-cost design tools.

Some structured ASIC vendors focus exclusively on generic designs or logic-heavy designs. This class of design tends to be very price competitive. Xilinx is now able to offer a more compelling solution than any structured ASIC vendor with its Spartan-3™ EasyPath FPGAs, which are priced below these structured ASICs.

For designs that require a lot of IP and system integration such as PowerPC processors, DSP, high-speed I/O, or Ethernet MACs, translation to a structured ASIC vendor often requires a re-validation of the IP on the vendor’s silicon platform of choice. With Xilinx Virtex-4™ EasyPath solutions, you get the same wide range of validated IP as with standard FPGAs. There is no additional fee required to migrate the IP to a volume solution.

The bottom line is that whether it is a generic design or an IP-centric design, EasyPath FPGAs offer very competitive and cost-effective solutions for high-volume migration when compared to structured ASICs, all from a single trusted supplier. Migration to structured ASICs, on the other hand, can pose a number of challenges.

Conversion-Free Methodology
The vast majority of IC design starts begin with FPGA prototyping, followed by a conversion to a volume solution. This carries the inherent risk of redesigning and reverifying the design in the target architecture, along with the related costs of re-spins, conversions, and a host of other design issues. The conversion from FPGA to structured ASIC is not seamless; rather, it is fraught with risks.

One issue faced by structured ASIC companies revolves around the mapping of memories from an FPGA to a structured ASIC. FPGAs generally tend to have columnar memory architectures and offer an efficient means to form larger memory structures when required. On the other hand, the use of distributed memory blocks in some structured ASIC architectures can pose problems when large contiguous blocks are required by the design.

The need to join together blocks that are physically separated to form a larger block that is logically monolithic can increase routing congestion. This can not only potentially deteriorate the access times of those memory structures but also leave fewer routing resources available for logic, thus impacting design performance.

With EasyPath FPGAs, there is no conversion. EasyPath FPGAs are exactly the same as the standard FPGAs on which a design is prototyped – the only difference is that the latter are completely programmable, while the former are not. As a result, memory mapping and performance achieved in an EasyPath FPGA is identical to that achieved in a standard FPGA.

Another problem that some structured ASIC companies face has to do with pad limitations. It is fairly well known that as process nodes shrink, more and more designs become pad-limited in ASICs. To get an adequate number of pads, structured ASIC vendors sometimes have to grow their die size and increase the effective cost to end customers. This problem is compounded by the fact that structured ASIC I/Os tend not to be as flexible as FPGA I/Os.

To keep I/O structures small and less area-intensive, structured ASIC vendors have to make some difficult choices about what standards they want to address and how. In cases where designs require large buses of input and output I/Os (for example, SSTL2 buses for SDRAM, or HSTL buses for certain telecom protocols), the limitations in the design of I/O structures can make it difficult to achieve pin compatibility in the FPGA-to-ASIC conversion. The end result is that customers have to either re-spin their board or migrate to a larger device – both unpalatable options. None of these are issues with EasyPath FPGAs because of the one-toone mapping between them and standard FPGAs.

Apart from memory and I/Os, there is a whole other host of issues, including difficulties with IP translation and testing, when moving from FPGAs to structured ASICs. FPGA cost reduction plans that involve converting to structured ASICs in order to get a smaller die are likely to trigger design changes and schedule risks.

The EasyPath solution, on the other hand, is neither an ASIC conversion nor a mask-programmed FPGA. No conversion or silicon differences are involved, so there are no long lead times, no timing or pinout changes, no need for product qualification, no lost feature support, and no risk of a design failure. In addition to eliminating any hidden design or qualification expenses and the risks of ASIC conversions, EasyPath FPGAs are delivered in eight weeks in production volume, allowing you the benefits of faster time to market or more time to perfect your designs.

Unprecedented Flexibility
One of the major advantages of FPGAs over ASICs is the flexibility to make design changes in case of a specification change or a design error. Traditionally, customers have had to forgo this advantage as they move from FPGAs to an inflexible custom solution like standard cell or structured ASICs. Now, with EasyPath FPGAs, Xilinx offers two flexibility features that allow you to enjoy some of the FPGA advantages when you go to volume production at prices below structured ASICs.

Spartan-3 and Virtex-4 EasyPath FPGAs enable you to buy a custom device that supports two applications – one for diagnostic testing and one for the actual application. EasyPath FPGAs can now be tested for two designs, or two variations of the same design. This means that you can now enjoy greater flexibility while also saving on BOM and inventory costs. For example, you can use one bitstream to perform system diagnostics on the entire system and then load the second application-specific bitstream. This reduces associated manufacturing system costs.

Xilinx offers EasyPath FPGA devices with LUTs and I/Os tested for drive strengths and slew rates, allowing revisions like engineering change orders at the LUT or I/O level. In many instances, even after the customer design is fully functional and certified, flexibility with I/O drive strengths and slew rates is critical.

For instance, a line card in a router might need to have the drive strength (and slew rate) adjusted a notch or two depending on what load it sees. EasyPath customers can choose to have a range of drive strengths available to them for certain I/Os. The unique flexibility is implemented on an asneeded basis. This eliminates any re-spin and conversionrelated engineering effort, delay, and expenses associated with ASICs and structured ASICs.

Conclusion
EasyPath FPGAs from Xilinx offer a seamless one-for-one, no-conversion volume reduction solution across an industryleading portfolio of product families. The comparison between EasyPath FPGAs and structured ASICs shown in Table 1 illustrates why EasyPath is a much superior solution. Unlike structured ASICs, EasyPath customers can get to production volumes much faster and now can do so at lower prices as well.

For more information about the nextgeneration EasyPath FPGAs, please visit www.xilinx.com/easypath/, where you can get information on the platform support, flexibility features, and use an online cost calculator to find out why EasyPath FPGAs are the lowest total cost solution in the industry.

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