過去 7 日間に出たアンサー
AR #15505 - System Generator for DSP - How do I create a design with bidirectional ports?
最終更新日: 2008-08-20 00:00:00.0
AR #29055 - LogiCORE CORDIC v3.0 - CORDIC コアは Virtex-5、Spartan-3A、または Spartan-3A DSP で使用可能か
最終更新日: 2008-08-20 00:00:00.0
AR #30409 - LogiCORE Complex Multiplier v2.1 - Is the Complex Multiplier Core available for Virtex-5, Spartan-3E, Spartan-3A, or Spartan-3A DSP?
最終更新日: 2008-08-20 00:00:00.0
AR #21591 - LogiCORE Complex Multiplier - Release Notes and Known Issues
最終更新日: 2008-08-20 00:00:00.0
AR #30162 - LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) - Release Notes and Known Issues
最終更新日: 2008-08-20 00:00:00.0
AR #31456 - LogiCORE Cascaded Integrator Comb Compiler (CIC Compiler) v1.2 - Why do I see different behavior in post-PAR simulation compared to behavioral? Why do I receive incorrect results when I gate my input sample rate with the ND and CE signals?
最終更新日: 2008-08-20 00:00:00.0
AR #31507 - 10.1 iMPACT - JTAG Tap states are incorrect in Debug Scan Chain GUI
最終更新日: 2008-08-20 00:00:00.0
AR #31508 - Virtex-5 GTP RocketIO - TXKERR meaning for a 2-byte interface
最終更新日: 2008-08-20 00:00:00.0
AR #31509 - Virtex-5 GTX RocketIO - TXKERR meaning for a 4-byte interface
最終更新日: 2008-08-20 00:00:00.0
AR #30101 - LogiCORE IP-DSP Horizontal Basic IP - What do I do if my IP is no longer available in ISE 10.1? Why do I receive an error indicating that my IP cannot be found after updating to ISE 10.1?
最終更新日: 2008-08-20 00:00:00.0
AR #30159 - LogiCORE Accumulator v7.0 - Why is the Accumulator v7.0 no longer available in ISE 10.1? Why do I receive an error indicating that my Accumulator v7.0 cannot be found after updating to ISE 10.1?
最終更新日: 2008-08-20 00:00:00.0
AR #30660 - LogiCORE Adder Subtracter v7.0 - Why is the Adder_Subtracter v7.0 no longer available in ISE 10.1? Why do I receive an error indicating my Adder_Subtracter v7.0 cannot be found after updating to ISE 10.1?
最終更新日: 2008-08-20 00:00:00.0
AR #31515 - LogiCORE Binary Counter v8.0 - Is the Binary Counter core available for Virtex-5, Spartan-3A, or Spartan-3A DSP?
最終更新日: 2008-08-20 00:00:00.0
AR #23517 - LogiCore Linear Feedback Shift Register (LFSR) v3.0 - Is the Linear Feedback Shift Register (LFSR) Core available for Virtex-4, Virtex-5, Spartan-3E, Spartan-3A, or Spartan-3A DSP?
最終更新日: 2008-08-20 00:00:00.0
AR #31516 - LogiCORE Comparator v8.0 - Is the Comparator Core available for Virtex-5, Spartan-3A, or Spartan-3A DSP?
最終更新日: 2008-08-20 00:00:00.0
AR #30804 - LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) - Is the Sine-Cosine Look-Up Table (Sin Cos LUT) Core available for Virtex-5, Spartan-3A, or Spartan-3A DSP?
最終更新日: 2008-08-20 00:00:00.0
AR #31378 - LogiCORE Block Memory Generator v2.7 - BitGen DRC warnings are produced when DOA is unused and DIA is tied to ground
最終更新日: 2008-08-20 00:00:00.0
AR #31380 - LogiCORE FIFO Generator v4.3 - The first word does not fall through in structural simulation of a Common Clock block RAM with FWFT
最終更新日: 2008-08-20 00:00:00.0
AR #31381 - LogiCORE FIFO Generator v4.3 - Empty flag does not assert in Common Clock (block RAM based) behavioral model simulation
最終更新日: 2008-08-20 00:00:00.0
AR #17706 - 9.1i PrimeTime - Trace と PrimeTime でのクロック スキューの違いについて
最終更新日: 2008-08-19 00:00:00.0
AR #23788 - Virtex-5 - スピード ファイルの改訂履歴
最終更新日: 2008-08-18 00:00:00.0
AR #24981 - Spartan-3A/AN - ファミリの改定履歴について
最終更新日: 2008-08-18 00:00:00.0
AR #29297 - LogiCORE Cascaded Integrator Comb Compiler (CIC Compiler) - リリース ノートおよび既知の問題
最終更新日: 2008-08-18 00:00:00.0
AR #29564 - 10.1 EDK、MPMC v4.01.a - MPMC2 のデザインを MPMC v3.00a 以降のデザインにアップグレードする方法
最終更新日: 2008-08-18 00:00:00.0
AR #30460 - 10.1i Timing Analyzer/Floorplan Editor - Cross-probing with non-updated NCD shows incorrect path
最終更新日: 2008-08-18 00:00:00.0
AR #30335 - 10.1 Timing Analyzer/ Constraints Editor/Floorplan Editor/PACE - Launching via command line causes multiple issues (crashes to incorrect files)
最終更新日: 2008-08-18 00:00:00.0
AR #30277 - 10.1 EDK - What patches are currently available for the EDK tools?
最終更新日: 2008-08-18 00:00:00.0
AR #29393 - Spartan-3A DSP - スピード ファイルの改訂履歴
最終更新日: 2008-08-18 00:00:00.0
AR #31124 - 10.1 Timing Analyzer - Standalone version launches when TWX file is not specified
最終更新日: 2008-08-18 00:00:00.0
AR #31216 - 10.1.02 System Generator for DSP - Release Notes, README, and Known Issues List
最終更新日: 2008-08-18 00:00:00.0
AR #31276 - 10.1.02 Timing Analyzer - Incorrect clock skew reported
最終更新日: 2008-08-18 00:00:00.0
AR #31406 - ModelSim, SecureIP - Warning/Error message from design points to protected region with ModelSim 6.3c and above
最終更新日: 2008-08-18 00:00:00.0
AR #31455 - 10.1.02 System Generator for DSP - When I use the CIC Compiler filter with an input data rate less than the system clock rate controlled by ND, I see mismatches between the simulation results in System Generator vs. hardware co-simulation
最終更新日: 2008-08-18 00:00:00.0
AR #31462 - 10.1 Spartan-3A PAR - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair
最終更新日: 2008-08-18 00:00:00.0
AR #31404 - 10.1 PlanAhead - What does the "Total Heap Size" in the right bottom corner mean?
最終更新日: 2008-08-18 00:00:00.0
AR #31442 - 10.1 EDK - I cannot add my custom IP core to my EDK design
最終更新日: 2008-08-18 00:00:00.0
AR #31500 - 10.1 Virtex-5 Route - MGT clock routing in LX330T does not use dedicated routing
最終更新日: 2008-08-18 00:00:00.0
AR #31504 - 10.1 Virtex-4 PLACE - Design fails to either fit or route due to poor clock region allocation
最終更新日: 2008-08-18 00:00:00.0
AR #31503 - 10.1 Virtex-5 PAR - ERROR:Route:472 - This design is unrouteable
最終更新日: 2008-08-18 00:00:00.0
AR #23716 - 9.1i EDK - XPS の makefile を最新バージョンの Cygwin の make ユーティリティ (3.81) で使用するとエラーが発生する
最終更新日: 2008-08-15 00:00:00.0
AR #24367 - Virtex-5 GTP RocketIO - Virtex-5 GTP トランシーバに関するアンサーのリスト
最終更新日: 2008-08-15 00:00:00.0
AR #29469 - LogiCORE Enpoint v3.6 for PCI Express - 9.2i IP アップデート (9.2i_IP2) のリリース ノートと既知の問題
最終更新日: 2008-08-15 00:00:00.0
AR #30980 - Endpoint Block Plus Wrapper v1.8 for PCI Express - Release Notes and Known Issues for ISE 10.1 IP Update 2 (IP_10.1.2)
最終更新日: 2008-08-15 00:00:00.0
AR #31457 - Virtex-5 GTX RocketIO - SATA Spread Spectrum Clocking attribute changes
最終更新日: 2008-08-15 00:00:00.0
AR #31458 - Virtex-5 GTX RocketIO - Answer Record List
最終更新日: 2008-08-15 00:00:00.0
AR #31461 - 10.1 Virtex-5 PAR - Clock placer might miscalculate the clock region used by EMAC and PPC components
最終更新日: 2008-08-15 00:00:00.0
AR #31463 - 10.1 Virtex-5 PAR - Placer does not place PLL and related DCM in the same tile
最終更新日: 2008-08-15 00:00:00.0
AR #31397 - Platform Cable USB - "A service installation section in this INF is invalid..."
最終更新日: 2008-08-14 00:00:00.0
AR #31444 - 10.1 EDK, MPMC v4.00.a - MPMC calibration fails in simulation with Virtex-4 DDR/DDR2 PHY
最終更新日: 2008-08-14 00:00:00.0
AR #31445 - 10.1 EDK, MPMC v4.00.a - ncelab: *F,CUMSTS: Timescale directive missing on one or more modules
最終更新日: 2008-08-14 00:00:00.0
AR #31446 - 10.1 EDK, ppc440mc_ddr2 - How do I use the ppc440mc_ddr2 signal MI_MCCLKDIV2?
最終更新日: 2008-08-14 00:00:00.0
AR #31447 - 10.1 EDK, ppc440mc_ddr2 - Does the MI_MCRESET signal need to be an external input?
最終更新日: 2008-08-14 00:00:00.0
AR #31448 - 10.1 EDK, MPMC v4.00.a - What is the maximum memory size that MPMC supports?
最終更新日: 2008-08-14 00:00:00.0
AR #31450 - 10.1 EDK, ppc440mc_ddr2 - Calibration hangs in stage 3 during simulation
最終更新日: 2008-08-14 00:00:00.0
AR #31449 - 10.1 EDK, ppc440mc_ddr2 - tRFC is violated during callibration
最終更新日: 2008-08-14 00:00:00.0
AR #31452 - 10.1 ChipScope Pro IBERT - When I open the cable I am asked to update my DRP settings, even though the design is unchanged
最終更新日: 2008-08-14 00:00:00.0
AR #31453 - 10.1 iMPACT - There is no "Read Protect" option available for my CoolRunner-II device
最終更新日: 2008-08-14 00:00:00.0
AR #31454 - 10.1.02 System Generator for DSP - For a multi-channel implementation, why is the FIR Compiler Chan_In output offset by a clock cycle from the actual channel it is accepting?
最終更新日: 2008-08-14 00:00:00.0