昨日出たアンサー
AR #6537 - Simulation, UniSim, SimPrim - How do I use the "glbl.v" module in a Verilog simulation?
最終更新日: 2008-10-09 00:00:00.0
AR #5666 - Virtex Configuration - Configuring multiple Virtex devices in SelectMAP mode
最終更新日: 2008-10-09 00:00:00.0
AR #5021 - JTAG - Is a bitstream generated for JTAG configuration the same as a bitstream for other configuration modes?
最終更新日: 2008-10-09 00:00:00.0
AR #4423 - JTAG - Testing support in Xilinx software and third-party JTAG software suppliers
最終更新日: 2008-10-09 00:00:00.0
AR #11713 - Virtex-E/-II/-II Pro - Maximum number of simultaneously switching outputs per Power/Ground pair (SSO guidelines)
最終更新日: 2008-10-09 00:00:00.0
AR #11602 - Virtex-II/Pro - LVPECL の終端設定について
最終更新日: 2004-01-25 00:00:00.0
AR #10427 - 制約 - FROM:TO 制約を使用する場合について
最終更新日: 2008-06-02 00:00:00.0
AR #8484 - Java API - Where can I acquire the JBits API for Virtex?
最終更新日: 2008-10-09 00:00:00.0
AR #9762 - Virtex/-E/-II/-II Pro, Spartan-II/-IIE - Can HSTL signals be operated at VCCO = 1.8V?
最終更新日: 2008-10-09 00:00:00.0
AR #9097 - Virtex-II/-II Pro, BUFGMUX - What is the setup time for the select or enable signal of BUFGCE/BUFGMUX?
最終更新日: 2008-10-09 00:00:00.0
AR #13397 - Virtex-II、DCM - DCM のサイクル間の出力ジッタ
最終更新日: 2007-01-29 00:00:00.0
AR #13716 - Virtex-II - Will the weak-keeper circuitry at the I/Os function with DCI-terminated standards?
最終更新日: 2002-02-01 00:00:00.0
AR #13935 - Virtex-II Pro RocketIO - シリアル ATA (SATA) について
最終更新日: 2008-05-15 00:00:00.0
AR #14748 - Virtex-II Pro RocketIO - How should unused RocketIO transceiver pins be handled?
最終更新日: 2008-10-09 00:00:00.0
AR #18834 - Virtex-II - Speeds file revision history
最終更新日: 2008-10-09 00:00:00.0
AR #19515 - Virtex-II Pro - スピード ファイルの改訂履歴
最終更新日: 2007-04-11 00:00:00.0
AR #19866 - Virtex-II/-II Pro, Spartan-3 Configuration - FPGAs configured in serial mode do not wake up to function correctly even though I have DriveDONE set for the last device in the daisy chain
最終更新日: 2008-10-09 00:00:00.0
AR #13213 - UniSim, SimPrim, Simulation - How do I simulate the DCM without connecting the CLK Feedback (CLKFB) port? (VHDL)
最終更新日: 2008-09-27 00:00:00.0
AR #21632 - How do I integrate per pin parasitic package data (in the .pkg file) provided in the IBIS archive into the IBIS file? How do I ensure that the latest IBIS model and package models are being adopted by IBISWriter for generating custom IBIS file?
最終更新日: 2008-10-09 00:00:00.0
AR #31773 - 10.1.03 ISE - Installation Instructions and Release Notes for Language Templates Update
最終更新日: 2008-10-09 00:00:00.0
AR #31752 - 10.1 NGDBUILD - "WARNING:ConstraintSystem:85 -Constraint %s: This constraint will be ignored because %s could not be found"
最終更新日: 2008-10-09 00:00:00.0
AR #31775 - 10.1 EDK - (920): Internal error: ../../../src/vcom/genexpr.c(6444)
最終更新日: 2008-10-09 00:00:00.0
AR #31780 - 10.1 ChipScope Pro - Master Xilinx Answer for ChipScope 10.1 and Service Packs
最終更新日: 2008-10-09 00:00:00.0
AR #31779 - 10.1SP3 ISim - "WARNING:Simulator:648 - "unisim_virtex5_SMODEL_isim.vhd" Line %s. Instance gtp_dual_fast/gtx_dual_fast is unbound"
最終更新日: 2008-10-09 00:00:00.0
AR #31776 - Endpoint Block Plus Wrapper v1.9 for PCI Express - On a lane reversed x8 link, back-to-back ACK issue causes TX lock up
最終更新日: 2008-10-09 00:00:00.0
AR #30213 - 10.1 EDK, opb_mch_sdram_v1.01.b - Controller hangs during burst transactions
最終更新日: 2008-10-09 00:00:00.0
AR #29762 - 10.1 EDK, PLBv46 - PLBv46 does not allow more than 16 masters or 16 slaves on the bus
最終更新日: 2008-10-09 00:00:00.0
AR #31751 - 10.1 Timing Analyzer, Spartan-3A, 3A DSP, or 3AN - A warning about the minimum period for the clk0 output of the DCM period being too small is issued
最終更新日: 2008-10-09 00:00:00.0
AR #31781 - Virtex-5 RocketIO GTP - DRP reads PCS_COM_CFG incorrectly in simulation
最終更新日: 2008-10-09 00:00:00.0