7 Series FPGAs Integrated Block for PCI Express Product Guide (PG054) - 3.3 English

Document ID: PG054
Release Date: 2022-12-23
Version: 3.3 English

7 Series FPGAs Integrated Block for PCI Express Product Guide
IP Facts
Introduction
Features
Overview
Feature Summary
Applications
Licensing and Ordering
Product Specification
Standards Compliance
Resource Utilization
Minimum Device Requirements
Core Interfaces
System Interface
PCI Express Interface
Transaction Interface
Common Interface
Transmit Interface
Receive Interface
Physical Layer Interface
Configuration Interface
Interrupt Interface Signals
Error Reporting Signals
Dynamic Reconfiguration Port Interface
Internal Port Interface
Internal Configuration Access Port Interface
PCI Configuration Space
Designing with the Core
General Design Guidelines
Designing with the 64-Bit Transaction Layer Interface
TLP Format on the AXI4-Stream Interface
Transmitting Outbound Packets
Basic TLP Transmit Operation
Presenting Back-to-Back Transactions on the Transmit Interface
Source Throttling on the Transmit Datapath
Destination Throttling of the Transmit Datapath
Discontinuing Transmission of Transaction by Source
Discarding of Transaction by Destination
Packet Data Poisoning on the Transmit AXI4-Stream Interface
Streaming Mode for Transactions on the Transmit Interface
Using ECRC Generation
Receiving Inbound Packets
Basic TLP Receive Operation
Throttling the Datapath on the Receive AXI4-Stream Interface
Receiving Back-to-Back Transactions on the Receive Interface
Packet Re-ordering on Receive Interface
Packet Data Poisoning and TLP Digest on the 64-Bit Receive AXI4-Stream Interface
ECRC Error on the 64-Bit Receive AXI4-Stream Interface
Packet Base Address Register Hit on the Receive AXI4-Stream Interface
Packet Transfer During Link-Down Event on Receive AXI4-Stream Interface
Designing with the 128-Bit Transaction Layer Interface
TLP Format in the AXI4-Stream Interface
Transmitting Outbound Packets
Basic TLP Transmit Operation
Presenting Back-to-Back Transactions on the Transmit Interface
Source Throttling on the Transmit Datapath
Destination Throttling of the Transmit Datapath
Discontinuing Transmission of Transaction by Source
Discarding of Transaction by Destination
Packet Data Poisoning on the Transmit AXI4-Stream Interface
Streaming Mode for Transactions on the Transmit Interface
Using ECRC Generation (128-Bit Interface)
Receiving Inbound Packets
Basic TLP Receive Operation
Throttling the Datapath on the Receive Interface
Receiving Back-to-Back Transactions on the Receive Interface
Receiving Straddled Packets on the Receive AXI4-Stream Interface
Packet Re-ordering on the Receive AXI4-Stream Interface
Packet Data Poisoning and TLP Digest on the 128-Bit Receive AXI4-Stream Interface
ECRC Error on the 128-Bit Receive AXI4-Stream Interface
Packet Base Address Register Hit on the Receive AXI4-Stream Interface
Packet Transfer Discontinue on the Receive AXI4-Stream Interface
Transaction Processing on the Receive AXI4-Stream Interface
Atomic Operations
Core Buffering and Flow Control
Maximum Payload Size
Transmit Buffers
Receiver Flow Control Credits Available
Flow Control Credit Information
Receive Credit Flow Control Information
Transmit Credit Flow Control Information
Designing with the Physical Layer Control and Status Interface
Design Considerations for a Directed Link Change
Directed Link Width Change
Directed Link Speed Change
Directed Link Width and Speed Change
Designing with Configuration Space Registers and Configuration Interface
Registers Mapped Directly onto the Configuration Interface
Device Control and Status Register Definitions
cfg_bus_number[7:0], cfg_device_number[4:0], cfg_function_number[2:0]
cfg_status[15:0]
cfg_command[15:0]
cfg_dstatus[15:0]
cfg_dcommand[15:0]
cfg_lstatus[15:0]
cfg_lcommand[15:0]
cfg_dcommand2[15:0]
Core Response to Command Register Settings
Status Register Response to Error Conditions
Accessing Registers through the Configuration Port
Optional PCI Express Extended Capabilities
Xilinx Defined Vendor Specific Capability
Loopback Control Register (Offset 08h)
Loopback Status Register (Offset 0Ch)
Loopback Error Count Register 1 (Offset 10h)
Loopback Error Count Register 2 (Offset 14h)
Advanced Error Reporting Capability
Resizable BAR Capability
User-Implemented Configuration Space
PCI Configuration Space
PCI Express Extended Configuration Space
Additional Packet Handling Requirements
Generation of Completions
Tracking Non-Posted Requests and Inbound Completions
Handling Message TLPs
Root Port Configuration
Reporting User Error Conditions
Error Types
Completion Timeouts
Unexpected Completions
Completer Abort
Unsupported Request
ECRC Error
AER Requirements
Resizable BAR Implementation-Specific Information (Endpoint Only)
Error Detection
Power Management
Active State Power Management
Programmed Power Management
PPM L0 State
PPM L1 State
PPM L3 State
Generating Interrupt Requests
Legacy Interrupt Mode
MSI Mode
MSI-X Mode
Link Training: 2-Lane, 4-Lane, and 8-Lane Components
Link Partner Supports Fewer Lanes
Lane Becomes Faulty
Lane Reversal
Using the Dynamic Reconfiguration Port Interface
Writing and Reading the DRP Interface
Other Considerations for the DRP Interface
DRP Address Map
Tandem Configuration
Supported Devices
Overview of Tandem Tool Flow
Tandem PROM
Tandem PROM KC705 Example Tool Flow
T a nde m P R O M Summary
Tandem PCIe
Tandem PCIe KC705 Example Tool Flow
Loading Stage 2 Through PCI Express
Tandem PCIe Summary
Using Tandem With a User Hardware Design
Method 1 – Using the Existing PCI Express Example Design
Method 2 – Migrating the PCIe Design into a New Vivado Project
Tandem Configuration RTL Design
MUXin g Criti c a l Inpu t s
Tandem Completer
Tandem Configuration Logic
User Application Handshake
Tandem Configuration Details
I/ O Beh a vior
Configu r a t io n Pi n Beh a vior
Configuration P e r si s t (Tandem PROM Only)
P R O M Selection
P r og r ammin g th e D e vice
Encrypted Bitstreams
Multiboot
Increasing the Loading Clock Frequency for Zynq-7000 Devices
Changing the Bitstream Load Frequency
Tandem PROM/PCIe Resource Restrictions
Moving the PCIe Reset Pin
Non-Project Flow
Simulating the Tandem IP Core
Calculating Bitstream Load Time for Tandem
Example 1
Example 2
Using Bitstream Compression
Other Bitstream Load Time Considerations
Case 1: Without ATX Supply
Case 2: With ATX Supply
Sample Bitstream Sizes
Clocking
Synchronous and Non-Synchronous Clocking
Resets
Protocol Layers
Transaction Layer
Data Link Layer
Physical Layer
Configuration Management
Shared Logic
Shared Clocking
Limitations
Shared GT_COMMON
Shared GT_COMMON Use Cases with GTX and GTP
Limitations
Shared GT_COMMON and Clocking
Internal Shared GT_COMMON and Clocking
Clocking Interface
FPGA Configuration
Configuration Terminology
Configuration Access Time
Configuration Access Specification Requirements
Board Power in Real-World Systems
Hot Plug Systems
Recommendations
FPGA Configuration Times for 7 Series Devices
Sample Issue Analysis
Failed FPGA Recognition
Successful FPGA Recognition
Workarounds for Closed Systems
Design Flow Steps
Customizing and Generating the Core
Base Mode
Basic
Component Name
Mode
Device / Port Type
PCIe Block Location
Xilinx Development Board
Silicon Revision
Number of Lanes
Maximum Link Speed
AXI Interface Frequency
AXI Interface Width
Reference Clock Frequency
Tandem Configuration
PIPE Mode Simulations
Enable External GT Channel DRP
Enable External Startup Primitive
Additional Transceiver Control and Status Ports
Identifiers (IDs)
ID Initial Values
Class Code
Class Code Look-up Assistant
Cardbus CIS Pointer
Base Address Registers (BARs)
Base Address Register Overview
Expansion ROM Base Address Register
Managing Base Address Register Settings
Disabling Unused Resources
Core Capabilities
Capabilities Register
Device Capabilities Register
Block RAM Configuration Options
Device Capabilities 2 Register
Interrupts
Legacy Interrupt Settings
MSI Capabilities
Advanced Mode
Basic
Identifiers (IDs)
Base Address Registers (BARs)
Core Capabilities
Device Capabilities Register
Device Capabilities Register
Link Registers
Link Capabilities Register
Link Control Register
Link Status Register
Configuration Register (Only in Root Port Configuration)
Root Capabilities Register
Slot Control Capabilities Register
Interrupts
MSI-X Capabilities
Power Management
Power Consumption
Power Dissipated
Extended Capabilities
Device Serial Number Capability
Virtual Channel Capability
Vendor Specific Capability
User-Defined Configuration Capabilities: Endpoint Configuration Only
Extended Capabilities 2
AER Capability
RBAR Capabilities
ECRC
TL Settings
Transaction Layer Module
DL and PL Settings
Link Layer Module
Advanced Physical Layer
Shared Logic
Core Interface Parameters
PL Interface
Error Reporting
Config Management Interface
Config CTRL Interface
Config Status Interface
Receive Msg Interface
Config FC Interface
Add. Debug Options
Output Generation
Endpoint Configuration
Root Port Configuration
Constraining the Core
Device, Package, and Speed Grade Selections
User Timing Constraints
User Physical Constraints
Core Pinout and I/O Constraints
Core Physical Constraints
Core Timing Constraints
Device Selection
Core I/O Assignments
Core Physical Constraints
Core Timing Constraints
Relocating the Integrated Block Core
Available Integrated Blocks for PCIe
Recommended GT Locations
Zynq-7000 Devices
Virtex-7 Devices
Kintex-7 Devices
Artix-7 Devices
Simulation
Simulating with Tandem Configurations
PIPE Mode Simulations
Post-Synthesis Netlist Functional Simulation
Post-Implementation Netlist Functional Simulation
Synthesis and Implementation
Example Design
Integrated Block Endpoint Configuration Overview
Simulation Design Overview
Implementation Design Overview
Example Design Elements
Programmed Input/Output: Endpoint Example Design
System Overview
PIO Hardware
Base Address Register Support
Changing the Default BAR Settings
TLP Data Flow
Memory and I/O Write TLP Processing
Memory and I/O Read TLP Processing
PIO File Structure
PIO Application
Receive Path
Transmit Path
Endpoint Memory
PIO Operation
PIO Read Transaction
PIO Write Transaction
Device Utilization
Summary
Configurator Example Design
System Overview
Configurator Example Design Hardware
Configurator Block
Configurator ROM
PIO Master
Configurator File Structure
Summary
Generating the Core
Simulating the Example Design
Endpoint Configuration
Synthesizing and Implementing the Example Design
Directory and File Contents
Endpoint Solution
project_1/project_1.src/sources_1/ip/pcie_7x_0
pcie_7x_0
source
sim
synth
pcie_7x_0/source
pcie_7x_0/example_design
pcie_7x_0/simulation
pcie_7x_0/hierarchy.txt
pcie_7x_0/simulation/dsport
pcie_7x_0/simulation/functional
pcie_7x_0/simulation/tests
Root Port Solution
project_1/project_1.src/sources_1/ip/pcie_7x_0
pcie_7x_0
source
sim
synth
pcie_7x_0/source
pcie3_7x_0/example_design
pcie_7x_0/simulation/ep
pcie_7x_0/simulation/functional
Test Benches
Root Port Model Test Bench for Endpoint
Architecture
Simulating the Example Design
Scaled Simulation Timeouts
Test Selection
Output Logging
Parallel Test Programs
Test Description
Test Program: pio_writeReadBack_test0
Expanding the Root Port Model
Root Port Model TPI Task List
Endpoint Model Test Bench for Root Port
Architecture
Simulating the Example Design
Scaled Simulation Timeouts
Output Logging
Upgrading
Migrating to the Vivado Design Suite
Migration to 7 Series Devices
Core Capability Differences
Configuration Interface
Error Reporting Signals
ID Initial Values
Physical Layer Interface
Dynamic Reconfiguration Port Interface
TRN to AXI Migration Considerations
High-Level Summary
Step-by-Step Migration Guide
Signal Changes
Datapath DWORD Ordering
Start-Of-Frame Signaling
32-Bit and 64-Bit Interfaces
128-Bit Interface
Remainder/Strobe Signaling
64-Bit Transmit
64-Bit Receive
128-Bit Transmit
128-Bit Receive
Packet Transfer Discontinue on Receive
Packet Re-ordering on Receive
System Reset
Upgrading in the Vivado Design Suite
Parameter Changes
Port Changes
Debugging
Finding Help on Xilinx.com
Documentation
Solution Centers
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Link Analyzers
Third-Party Tools
LSPCI (Linux)
PCItree (Windows)
PCI-SIG Software Suites
Simulation Debug
PIO Simulator Expected Output
Compiling Simulation Libraries
Next Step
Hardware Debug
FPGA Configuration Time Debug
Link is Training Debug
FPGA Configuration Time Debug
Clock Debug
Debugging PCI Configuration Space Parameters
Application Requirements
Using a Link Analyzer to Debug Device Recognition Issues
Data Transfer Failing Debug
Identifying Errors
Transmit
Fatal Error Detected on Root or Link Partner
Fatal Error Not Detected
Receive
Non-Fatal Errors
Correctable Non-Fatal Errors
Uncorrectable Non-Fatal Errors
Next Steps
Additional Transceiver Control and Status Ports
Managing Receive-Buffer Space for Inbound Completions
General Considerations and Concepts
Completion Space
Maximum Request Size
Read Completion Boundary
Methods of Managing Completion Space
LIMIT_FC Method
PACKET_FC Method
RCB_FC Method
DATA_FC Method
STREAM_FC Method
PCIE_2_1 Port Descriptions
Clock and Reset Interface
Transaction Layer Interface
Block RAM Interface
GTX Transceiver Interface
GTX Transceiver Ports
PIPE per Lane Ports
Configuration Management Interface
Management Interface Ports
Error Reporting Ports
Interrupt Generation and Status Ports
Root Port Specific Ports
Received Message TLP Status Ports
Power Management Ports
Received Configuration TLP Status Ports
Configuration-Specific Register Ports
Miscellaneous Configuration Management Ports
Dynamic Reconfiguration Port Interface
TL2 Interface Ports
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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