Performance and Resource Utilization for Binary Counter v12.0

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_128_lut Fabric 128 false 1 UP false 8 CLK 631 160 270 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 494 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 308 199 277 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_18_lut Fabric 18 false 1 UP false 2 CLK 724 22 29 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 658 22 30 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_47_lut Fabric 47 false 1 UP false 2 CLK 658 25 73 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 369 8 0 1 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_128_lut Fabric 128 false 1 UP false 8 CLK 664 175 270 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 669 208 494 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 369 199 277 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_18_lut Fabric 18 false 1 UP false 2 CLK 938 21 29 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 730 22 30 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_47_lut Fabric 47 false 1 UP false 2 CLK 664 25 73 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 429 8 0 1 0 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 172 270 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 208 494 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 511 199 277 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1474 21 29 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1091 22 30 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1025 25 73 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 610 8 0 1 0 0 PRODUCTION 1.23 03-18-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_128_lut Fabric 128 false 1 UP false 8 CLK 636 160 270 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 636 209 494 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 308 199 277 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_18_lut Fabric 18 false 1 UP false 2 CLK 779 22 29 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 653 22 30 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_47_lut Fabric 47 false 1 UP false 2 CLK 658 25 73 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_48_dsp DSP48 48 false 1 UP false 2 CLK 544 0 0 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 544 0 0 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 369 8 0 1 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_128_lut Fabric 128 false 1 UP false 8 CLK 675 177 270 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 615 209 494 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 358 199 277 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_18_lut Fabric 18 false 1 UP false 2 CLK 938 21 29 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 713 22 30 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_47_lut Fabric 47 false 1 UP false 2 CLK 669 25 73 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_48_dsp DSP48 48 false 1 UP false 2 CLK 675 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 631 0 0 1 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 424 8 0 1 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_128_lut Fabric 128 false 1 UP false 8 CLK 790 176 270 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 209 494 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 440 199 277 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1249 19 29 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1113 22 30 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1047 25 73 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 599 8 0 1 0 0 PRODUCTION 1.23 03-18-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Implementation
Output_Width
Restrict_Count
Final_Count_Value
Count_Mode
Load
Latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_128_lut Fabric 128 false 1 UP false 8 CLK 872 176 270 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_128_lut_ld Fabric 128 false 1 UP true 8 CLK 872 208 494 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_128_lut_rc Fabric 128 true 5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A UP false 8 CLK 489 199 277 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_18_lut Fabric 18 false 1 UP false 2 CLK 1211 20 29 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_18_lut_updown Fabric 18 false 1 UPDOWN false 2 CLK 1030 22 30 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_47_lut Fabric 47 false 1 UP false 2 CLK 1047 25 73 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_48_dsp DSP48 48 false 1 UP false 2 CLK 833 0 0 1 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_48_dsp_ld DSP48 48 false 1 UP true 2 CLK 833 0 0 1 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_48_dsp_rc DSP48 48 true 05fd2624c UP false 2 CLK 625 8 0 1 0 0 PRODUCTION 1.25 05-09-2019

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Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

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