Virtex-4QV

耐放射線 Virtex®-4 QPro™-V FPGA DC 特性およびスイッチ特性

耐放射線強化Virtex®-4 QPro™-V ファミリのデータシート

This guide provides complete packing information for Virtex®-4 QPro™-V (QV) Radiation-Hardened FPGAs in 1.00-mm pitch ceramic flip-chip column grid array (CF) packages. Virtex-4 QV Radiation Hardened FPGAs are offered exclusively in ceramic flip-chip column grid array (CF) packages that are optimally designed for improved thermal cycle reliability.

This application note describes mitigation techniques using triple-module-redundancy (TMR) combined with configuration scrubbing for Xilinx®-specific block RAMs in high radiation environments. Also included is a design example demonstrating these mitigation techniques.

This application note discusses different aspects of single-event upsets and recommends appropriate mitigation schemes under each circumstance.

This application note describes the use of configuration scrubbing and readback in Virtex®-4 FPGAs for the purpose of detecting and correcting single-event upsets to the configuration memory array induced by cosmic rays.

This application note discusses self-hosting configuration management hardware setup for Xilinx® FPGAs for the purpose of detecting and correcting single-event upsets (SEUs) to the configuration memory array.

This application note describes mitigation techniques and corresponding design flow when using a Xilinx® FPGA with an embedded processor (specifically the PowerPC® 405 found in the Virtex®-4 FX family) in high-radiation environments.