Introduction to Verilog

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コース概要

FPGA デザイン カリキュラム パス

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Designing with PlanAhead

Virtex-4 デザイン

Virtex-5 LX および LXT デザイン

Design Techniques for Lower Cost

Introduction to VHDL

TMRTool

Advanced VHDL

関連情報

すべてのコース リスト

 

コースの解説

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

レベル

初級から中級

トレーニング時間

3 日間

参加対象

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

前提条件

• Basic digital design knowledge

ソフトウェア ツール

• ISE™ 9.1i
• Xilinx ISIM Simulator
• Synplicity Synplify Pro

このトレーニングに参加すると次のことが出来るようになります:

• Write RTL Verilog code for synthesis
• Write Verilog test fixtures for simulation
• Create a Finite State Machine (FSM) by using Verilog
• Target and optimize Xilinx FPGAs by using Verilog
• Use enhanced Verilog file I/O capability
• Run a timing simulation by using Xilinx Simprim libraries
• Create and manage designs by using the ISE software design environment

コース概要

1 日目

• Hardware Modeling Overview
• Verilog Language Concepts
• Memories, Modules, and Ports
• Lab 1: Building Hierarchy
• Introduction to Testbenches
• Lab 2: Verilog Simulation and RTL Verification
• Operators and Expressions

2 日目

• Data Flow-Level Modeling
• Lab 3: Memory
• Verilog Procedural Statements
• Controlled Operation Statements
• Lab 4: n-bit Binary Counter and RTL Verification
• Advanced Language Concepts
• Lab 5: Comparator

3 日目

• Tasks and Functions
• Lab 6: Arithmetic Logic Unit
• Finite State Machines
• Lab 7: Finite State Machines
• Targeting Xilinx FPGAs
• Lab 8: Calculator
• Advanced Verilog Testbenches
• Lab 9: Using Verilog File I/O

演習の解説

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.