録音版 e-ラーニング コース
ご都合の良いときにいつでも受講できる録音版 e-ラーニング コースを提供しています。ハイレベルなソフトウェア アップデートや ASIC から FPGA への特定のデバイス アーキテクチャに変換する方法などさまざまなコースが無償で受講いいただけます。ぜひ、ご覧ください!
FPGA デザイン コース
Basic FPGA Configuration
This is a two-module course. After completing this 50-minute, two-module course, you will be able to describe the FPGA configuration pins, choose an appropriate FPGA configuration scheme, connect multiple FPGAs into a configuration daisy chain, and describe currently available prototyping hardware.
- Part 1 の視聴
- Part 2 の視聴
基本 FPGA アーキテクチャ : Architecture Wizard と Floorplan Editor - ダウンロード
この約 30 分のコースを終了すると Architecture Wizard の用法を 2 つ以上理解し、Floorplan Editor の 2 つ特徴を理解して、ザイリンクス FPGA で効果的なピンの割り当てができるようになります。
Basic FPGA Architecture: Virtex-6 Memory and Clocking Resources - 視聴
After completing this 30-minute training, you will be able to fully utilize the Virtex®-6 distributed memory, block memory, and FIFO resources, use the Memory Interface Generator (MIG) to build a custom memory controller for your off-chip memory component.
Basic FPGA Architecture: Spartan-6 Memory and Clocking Resources - 視聴
After completing this 32-minute training you will be able to fully utilize the Spartan®-6 distributed and block memory resources, understand the features and limitations of the Spartan-6 dedicated memory controller block (MCB), use the Memory Interface Generator (MIG) to build your custom memory controller and design an appropriate interface to your off-chip memory component.
基本 FPGA アーキテクチャ : スライスおよび I/O リソース - ダウンロード
この 48 分のコースを視聴すると、Virtex-6 FPGA のスライス リソースの基礎、Virtex-4 FPGA の I/O リソースの基礎を理解することが出来るようになります。
ChipScope™ Pro Software (with labs) - 視聴
After completing this 27-minute course, you will be able to describe the value of the ChipScope Pro software, describe how it works, list available relevant cores, use the Core Generator and Core Inserter software, plan for debug, and debug with the ChipScope Pro software. Links to the labs are at the end of the recording.
Spartan®-3E FPGA Architecture - 視聴
After completing this 43-minute course, you will be able to describe how the architecture of the Spartan-3E FPGA differs from the architecture of the Spartan-3 FPGA, determine if the Spartan-3E FPGA architecture fits your application requirements, and describe the new features of the Spartan-3E FPGA platform.
Spartan-3 FPGA Architecture Overview - 視聴
After completing this 31-minute course, you will be able to describe the Spartan-3 architecture, its underlying technology and target markets, as well as its design entry, implementation, and verification software support features. You will also be able to describe the system solutions for DSP, MicroBlaze™ embedded processor, and communications connectivity.
Global Timing Constraints - Coming Soon
After completing this 15-minute course, you will be able to apply global timing constraints to a simple synchronous design and use the Constraints Editor to specify global timing constraints.
Area Constraints - 視聴
After completing this 27-minute course, you will be able to make an effective layout with area constraints, use area constraints to improve the speed of your design by grouping critical paths, use area constraints to localize (and maximize) your designs clocks, and use area constraints in an incremental design flow.
Timing Closure Flow - 視聴
After completing this 71-minute course, you will be able to describe the overall flow for achieving timing closure, specify the key elements in achieving timing closure, describe the importance of cores and coding for performance, list some of the key implementation options in timing closure, and state where to learn more about each step in the timing closure flow.
Achieving Breakthrough Performance in Virtex-4 FPGAs - 視聴
After completing this 57-minute course, you will be able to describe Virtex-4 FPGA advantages, discuss how to achieve optimum FPGA performance, and describe the Virtex-4 FPGA performance comparison methodology.
Clocking Techniques for Virtex-II FPGAs - 視聴
After completing this 34-minute course, you will be able to describe the features and limitations of the DCM, BUFGMUX, and global routing resources, and explain how to build a clock assignment strategy for your design.
SPI-4.2 - 視聴
After completing this 38-minute course, you will be able to identify the basics of the OSI 7 Layer Model, describe the protocol, specifications, and competitive advantages of the SPI-4.2 solution, and explain how the SPI-4.2 solution fits into the OSI 7 Layer Model.
IC Packaging - 視聴
After completing this 41-minute course, you will be able to determine the IC package that best meets your design goals, lList the various sources of heat generation in IC packages, identify and define critical thermal variables, and discuss Xilinx-provided specs to manage your thermal budget.
DDR-I SDRAM Memory Interface - 視聴
After completing this 35-minute course, you will be able to list the Virtex-II and Virtex-II Pro device features that enable high-speed memory interface design, calculate timing margins for the Virtex-II series DDR-I interface design, and access memory resources on the Xilinx website, including the Xilinx Memory Tool Kit.
FPGA Design for ASIC Users (with labs)
The FPGA Design for ASIC Users course will help you to create fast and efficient FPGA designs by leveraging your ASIC design experience.This course will help you avoid the most common design mistakes of FPGA designers. It will also help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs.
Power Estimation - 視聴
After completing this 29-minute training you will be able to: list the three phases of the design cycle where power calculations can be performed, estimate power consumption by using the XPower Estimator spreadsheet, estimate power consumption by using the XPower software utility.
Synthesis Options - 視聴
After completing this 45-minute training, you will be able to: identify synthesis tool options that can be used to increase performance and/or reduce your design size, describe an approach to using your synthesis tool to obtain higher performance and gain timing closure, use XST to get the most out of your HDL.
Core Generator - 視聴
After completing this 20-minute training you will be able to describe the differences between LogiCORE™ and AllianceCORE solutions, identify two benefits of using cores in your designs, create customized cores by using the CORE Generator software system GUI, instantiate cores into your HDL design, run behavioral simulation on a design that contains cores.
コネクティビティ デザイン コース
PCI Express® - 視聴
After completing this 45-minute course, you will be able to explain the background behind PCI Express, identify the differences between PCI and PCI Express, and describe a basic PCI Express Link, the different layers of a PCI Express device, and the Xilinx PCI Express solution.
DSP デザイン コース
System Generator イントロダクション - 7 つのモジュールを含む Zip ファイルをダウンロード
この 7 つのモジュールで構成された約 50 分のコースを視聴すると System Generator および Simulink を使い、メモリとコントローラを含んだ DSP デザインをザイリンクス FPGA にインプリメントすることができるようになります。ザイリンクス デバイス アーキテクチャに高度に最適化された FIR フィルタのインプリメントや、ザイリンクス ブロックセットを使用した DSP 固定小数点の仕様について理解できます。
AccelDSP™ ジャンプ スタート モジュール - 5 つのモジュールを含む Zip ファイルをダウンロード
この 5 つのモジュールで構成された 50 分のコースを視聴すると、AccelDSP 合成ツールを使用して合成できるように DSP アルゴリズム用に MATLAB® スクリプトを変更、MATLAB デザインでのビット幅の指定、モニタ、操作に加えて量子化の概念の理解、および MATLAB コーディング スタイルの変更とデザインの性能と効率を最適化することが出来るようになります。
CPLD デザイン コース
CoolRunner™-II CPLD: Clocking and I/O - 視聴
After completing this 15-minute course, you will be able to describe the clock divider and DualEDGE features of CoolRunner-II CPLDs, list applications that can benefit from these clocking features, and describe several solutions for special signaling and interface requirements.
ハードウェア記述言語
Basic HDL Coding Techniques
Part 1 - 視聴
This Basic HDL Coding Techniques, part 1 describes primary coding techniques for FPGAs. It included basic design guidelines that successful FPGA designers follow and explains proper coding techniques for combinatorial and registered logic. Microsoft Windows Media Player 8 or later is required to view this module.
Part 2 - 視聴
This Basic HDL Coding Techniques, part 2 describes primary coding techniques for FPGAs. It included basic design guidelines that successful FPGA designers follow, including Finite State Machine design and building pipeline stages. Microsoft Windows Media Player 8 or later is required to view this module.
Spartan-3 FPGA HDL Coding Techniques
Part 1 - 視聴
After completing this 30-minute module, you will be able to code properly for FPGA registers, SRLs, and other dedicated resources. These techniques will enable you to build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs.
Part 2 - 視聴
After completing this 30-minute module, you will be able to code properly for carry logic and memory resources. You will also be able to manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs.
Virtex®-5 FPGA HDL Coding Techniques
Part 1 - 視聴
After completing this 30-minute module, you will be able to code properly for Virtex-5 FPGA register resources. You will also be able to manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possible.
Part 2 - 視聴
After completing this 30-minute module, you will be able to code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA. You will also be able to manage your control signal usage so that you can build a high-speed FPGA design. Finally, you will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA.
Virtex®-6 & Spartan®-6 FPGA HDL Coding Techniques
Part 1 - 視聴
After completing this 30-minute module, you will be able to code your register resources so your design will have fewer control sets and run at a higher system speed, avoid the most common coding mistakes that reduce device utilization and system speed, anticipate how your design will map to the register resources.
Part 2 - 視聴
After completing this 30-minute module, you will be able to code your design so you can infer more of the dedicated hardware resources, avoid the most common coding mistakes which hurt device utilization, reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR).
受講後アンケート