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FPGA Design Flow using Vivado

Course Description This course provides professors with an introduction to digital design tool flow in Xilinx All Programmable devices using Vivado® Design software suite
Level Introductory
Duration 2 Days
Who should attend? Professors who are new to FPGAs or Xilinx technology and wish to use Xilinx All Programmable devices in digital design
Pre-requisites
  • Digital design experience
  • Basic HDL knowledge (VHDL or Verilog)

Skills Gained

After completing this workshop, you will be able to:

  • Describe the general Artix-7 All Programmable FPGA architecture
  • Understand the Vivado design flow
  • Create and debug HDL designs
  • Configure FPGA and verify hardware operation
  • Configure FPGA architecture features, such as Clock Manager, using the Architecture Wizard
  • Communicate design timing objectives through the use of Xilinx Design Constraints
  • Pinpoint design bottlenecks using the reports
  • Utilize synthesis options to improve performance
  • Create and integrate IP cores into design flow using IP Catalog
  • Use Logic Analyzer to perform on-chip verification
  • Perform simulation verifcation

Course Overview

Day 1:

  • 7-Series Architecture Overview
  • Lab 1: Vivado Design Flow
    • Use Vivado IDE to create a simple HDL design. Simulate the design using the XSIM HDL simulator available in Vivado design suite. Generate the bitstream and verify in hardware.
  • Synthesis Technique
  • Lab 2: Synthesizing a RTL Design
    • Synthesize a design with the default settings as well as other settings changed and observe the effect.
  • Implementation and Static Timing Analysis
  • Lab 3: Implementing the Design
    • Implement the synthesized design of previous lab, perform timing analysis, generate bitstream, download the bitstream and verify the functionality.

Day 2:

  • IP Integrator
  • Lab 4: Using the IP Catalog and IP Integrator
    • Use the IP Catalog to generate a clock resource and instantiate in a design. Use IP Integrate to generate a core and instantiate in the design.
  • Xilinx Design Constraints
  • Lab 5: Xilinx Design Constraints
    • Create a project with I/O Planning type, enter pin locations, and export it to the rtl. Then create the timing constraints and perform the timing analysis.
  • Hardware Debugging
  • Lab 6: Hardware Debugging
    • Use Mark Debug feature and also available Integrated Logic Analyzer(ILA) core (available in IP Catalog) to debug the hardware.

 

Common to ZedBoard and Zybo

ZedBoard

Zybo

Common to Nexys4 DDR, Nexys Video, and Basys3

Nexys4 DDR

Nexys Video

Basys3

Common to Nexys4 DDR, Nexys Video, and Basys3

Nexys4 DDR

Nexys Video

Basys3

Common to ZedBoard and ZYBO

ZedBoard

ZYBO

Common to Nexys4 and Basys3

Nexys4

Basys3