DSP Design Flow Workshop
Xilinx Requirements
Course Description
This course provides Professors with an introduction to FPGA-based DSP design using the Mathworks MATLAB®/Simulink® and Xilinx System Generator for DSP tools.
Level
Introductory
Training Duration
2 days
Who Should Attend?
Professors who are new to FPGA-based DSP design.
Prerequisites
- Digital Design Experience
- Basic HDL Knowledge (VHDL or Verilog)
- Basic experience with ISE™ Foundation™ software
- Understanding of fundamental DSP concepts
Skills Gained
After completing this training, you will be able to
- Understand why FPGAs lend to high-performance DSP design
- Understand the basics of Simulink
- Identify useful blocks in the System Generator blockset
- Model and Simulate a System Generator design in Simulink
- Understand the hardware impact of various parameter settings
- Understand the mechanisms for control
- Understand the underlying clocking for multirate systems
Course Outline
Day1
- Introduction: FPGAs for DSP
- Introduction to System Generator for DSP
- Simulink Basics
- Lab 1: Simulink Basics
- Basic Xilinx Design Capture
- Lab 2: Create a 12x8 MAC using System Generator for DSP
- Signal Routing
- Lab 3: Signal Routing
Day 2
- System Control
- Lab 4: Implementing System Control
- Multirate Systems
- Lab 5: Designing a MAC FIR
- Filter Design
- Lab 6: Designing a FIR Filter
Lab Descriptions
Lab 1 - Simulink Basics
Gain an Introduction to Simulink through the simulation of a sine wave, changing the sample rate to analyze the output.
Implement an hierarchical design via the creation of a simple filter.
Lab 2 - Create a 12x8 MAC using System Generator for DSP
Model a 12x8 Multiplier-Accumulator (MAC) using blocks from the Xilinx blockset and simulate it in Simulink. The MAC
will be used in a future lab for creating a MAC-based FIR filter.
Lab 3 - Signal Routing
Model and simulate logic for padding and un-padding data written to/read from FPGA block memory. This logic will be
used in a future lab for creating a MAC-based FIR filter.
Lab 4 - Implementing System Control
Create an address generator using basic Xilinx blocks and the m-code block. The address generator will be used in
a future lab for creating a MAC-based FIR filter.
Lab 5 - Designing a MAC FIR
Using elements from the previous labs, model a MAC-based FIR filter and simulate it in Simulink. Test the filter
in hardware via hardware-in-the-loop.
Lab 6 - Designing a FIR Filter
Generate the coefficients for a band-pass filter using the FDA Tool. Model the bandpass filter using the Xilinx
DA FIR and simulate it using white noise input. Test the filter in hardware via hardware-in-the-loop.
Attend a workshop near you
XUP members may access the workshop schedule to locate and register to attend workshops. University faculty may
sign up to
become members by creating a Xilinx Account.
Access workshop materials
XUP members may access the workshop materials from the table below for use in the engineering curriculum. University faculty may sign up to
become members by creating a Xilinx Account.
* Refer to the README files for a complete list of requirements
Contact XUP
For general questions or comments, please send an email to xup@xilinx.com
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