FPGA Design Flow Workshop
Xilinx Requirements
Course Description
This course provides Professors with an introduction to designing with Xilinx FPGAs using ISE® Foundation™ software.
Level
Introductory
Training Duration
2 days
Who Should Attend?
Professors who are new
to FPGAs or Xilinx technology and wish to develop
basic labs in digital design.
Prerequisites
- Digital design experience
- Basic HDL knowledge (VHDL or Verilog)
- Understanding of 8-bit controllers
Skills Gained
After completing this training, you will be able to:
- Describe the general FPGA architectures and the
design flow
- Configure FPGA architecture features, such as the DCM, using the Architecture Wizard
- Communicate design timing objectives through the use of global timing constraints
- Pinpoint design bottlenecks using the reports
- Utilize synthesis options to improve performance
- Understand the various implementation options
- Create and integrate IP cores into your design flow
using the Core Generator
- Use Chipscope™ Pro tool to perform on-chip verification
- Use the 8-bit PicoBlaze™ controller to interface to various board components
Course Outline
Day1
- Basic FPGA Architecture
- Xilinx Tool Flow
- Lab 1: Xilinx tool flow
- Architecture Wizard and PACE
- Lab 2: Architecture Wizard and PACE
- Reading Reports
- Global Timing Constraints
- Lab 3: Global Timing Constraints
- FPGA Design Techniques
Day 2
- Synchronous Design Techniques
- Floorplanner
- Synthesis Techniques
- Lab 4: Synthesis Techniques
- Implementation Options
- Core Generator System
- Lab 5: Core Generator System
- Chipscope-Pro
- Lab 6: Chipscope-Pro
Lab Descriptions
Lab 1 - Tool Flow
Introduction to FPGA design flow. Open a project containing the PicoBlaze 8-bit controller and simulate the design using the iSIM HDL simulator provided with the ISE Foundation software.
Lab 2 - Architecture Wizard and PACE
Use architecture wizard to configure and instantiate a Digital Clock manager into a PicoBlaze design. Assign pin locations with PACE. Implement design to generate a bitstream file. Download and test in hardware using hyperterminal.
Lab 3 - Global Timing Constraints
Enter and analyze the effects of global timing constraints on a simple PicoBlaze design. Download and test the design in hardware using hyperterminal.
Lab 4 - Synthesis with XST
Set various synthesis options to improve results for a simple PicoBlaze design. Download the design and test in hardware using hyperterminal.
Lab 5 - Core Generator
Generate the instruction ROM for a PicoBlaze design using CoreGen, initialized with instructions generated from the PicoBlaze assembler. Download and test in hardware.
Lab 6 - Chipscope-Pro
Use Chipscope-Pro to debug a simple PicoBlaze design using an ILA core.
Attend a workshop near you
XUP members may access the workshop schedule to locate and register to attend workshops. University faculty may
sign up to
become members by creating a Xilinx Account.
Access workshop materials
XUP members may access the workshop materials from the table below for use in the engineering curriculum. University faculty may sign up to
become members by creating a Xilinx Account.
* Refer to the README files for a complete list of requirements
Contact XUP
For general questions or comments, please send an email to xup@xilinx.com
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