October 1, 2021
This content is republished from the MicroZed Chronicles, with permission from the author.
There are several FPGA use cases where a softcore processor is beneficial to the overall solution. These can include anything from performing simple communication and configuration of IP cores using AXI Lite to complex GUI control and network management and security.
We have looked at many different processor types over the years, but we have never looked at a RISC-V implementation until today. In this blog, we are going to examine the newly released Bluespec RISC-V MCU which implements the RV32IM instruction set and provides the 32-bit RISC-V instruction and a hardware multiply / divide.
This RISC-V implementation is free to download and use (note that there is a 20 minute time limit of execution) and comes with an example application and documentation to start working with the Arty A7-100T board. In addition to the processor IP and reference designs, Bluespec also provides a pre-built tool chain.
To get started developing with this machine, we need to use a Linux machine or virtual machine running Linux.
Before we can start working with the RISC-V MCU, we need to install the Bluespec tool chain. A link to this will be provided on the download web page.
Once you have the .deb file downloaded, we can install it using the following commands:
sudo apt purge Bluespec-riscvtoolchain
sudo apt install ./Bluespec-riscvtoolchain_1.202109.1.1ubuntu1804-2_amd64.deb
With the tool chain installed, we can download and extract the MCU-Eval package. I also connected my Arty A7-100T to the Linux machine so that it was powered and ready for downloading a bitstream.
Enter the following commands to download and set up the RISC-V eval:
tar -xzvf RISCV32IM_MCU_Eval<release date>.tar.gz
In a second terminal window, open a UART terminal as provided.
Back in the main terminal window, enter the following command:
This will program the FPGA. The Bit file contains the application so execution will begin as soon as it is downloaded and programmed. You will notice that the UART terminal has a updated display showing the LED state and new messages.
So far so good but of course we will want to make our own applications or even make changes to the hardware design. Let’s take a look at how we do that.
To get started, we need to make a working directory and map it to the MCU_WORK area. Once we have done that, we can copy the demo application below.
cp -r $MCU_INSTALL/ref_apps/blinky $MCU_WORK/my_app
Now we can make changes to the C file. I added one extra Printf to show that it was rebuilding correctly. With the changes made as required, enter the following commands:
make clean; make all
Having merged the software ELF file into the RISC-V BRAM, we need a new processor to run it on now that we have a new software application.
We can create the base RISC-V processor in Vivado very simply using the following command:
MCU_INSTALL/utils/create_soc_project --project my_project \
--core RISCV32IM_MCU \
This will create a Vivado project based around the Bluespec RISC-V 32IM processor. We use this project as the base starting point if we need to make changes to this design (e.g., to add in new IP or interfaces).
In this case, I made no changes to the Vivado design.
Back in the command line, the next step is to build the bitstream which can be done using the following command:
MCU_INSTALL/utils/build_bitstream --project my_project \
--memhex $MCU_WORK/my_app/tcm.mem \
Once the build is complete, we can download the bitstream just like we did before. Remember to point the bitstream to the new location. This will be in the top location of your MCU_WORK directory.
If the second terminal is still running, you should see the new updated output appear.
As you can see, this flow is simple to get up and running. It only took about 10 minutes for me to get the tool installed and the first demo up and running on my board.
In terms of resource utilization, the overall implementation takes just 4523 LUTS, 328 FF, and 32 BRAM. According to Bluespec, the MCU can be reduced to under 2000 LUTs by removing the debug module, reducing the TCM size, and M instruction extension
This is an interesting development in the FPGA softcore universe. The deployment and project creation are very simple compared to some other RISC-V projects that I have put on the Arty board. This really impressed me. Now I’m wondering how easy it is to retarget the project to another board. That will be for another blog!