Performance and Resource Utilization for RAM-based Shift Register v12.0

Vivado Design Suite Release 2021.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_fl_128 Fixed_Length 16 128 CLK 636 64 32 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_fl_512 Fixed_Length 16 512 CLK 636 256 80 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_fl_64 Fixed_Length 16 64 CLK 636 32 32 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_vl_128 Variable_Length_Lossless 16 128 CLK 544 64 16 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_vl_512 Variable_Length_Lossless 16 512 CLK 363 272 16 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_vl_64 Variable_Length_Lossless 16 64 CLK 636 32 16 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_fl_128 Fixed_Length 16 128 CLK 735 64 32 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_fl_512 Fixed_Length 16 512 CLK 735 256 48 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_fl_64 Fixed_Length 16 64 CLK 735 32 32 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_vl_128 Variable_Length_Lossless 16 128 CLK 735 64 16 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_vl_512 Variable_Length_Lossless 16 512 CLK 538 272 16 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_vl_64 Variable_Length_Lossless 16 64 CLK 735 32 16 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_fl_128 Fixed_Length 16 128 CLK 872 64 32 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_fl_512 Fixed_Length 16 512 CLK 806 256 48 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_fl_64 Fixed_Length 16 64 CLK 872 32 32 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_vl_128 Variable_Length_Lossless 16 128 CLK 872 64 16 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_vl_512 Variable_Length_Lossless 16 512 CLK 664 272 16 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 1 kup_1_vl_64 Variable_Length_Lossless 16 64 CLK 872 32 16 0 0 0 PRODUCTION 1.28 02-27-2020

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_fl_128 Fixed_Length 16 128 CLK 680 64 48 0 0 0 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_fl_512 Fixed_Length 16 512 CLK 680 256 144 0 0 0 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_fl_64 Fixed_Length 16 64 CLK 680 32 32 0 0 0 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_vl_128 Variable_Length_Lossless 16 128 CLK 680 80 16 0 0 0 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_vl_512 Variable_Length_Lossless 16 512 CLK 680 336 16 0 0 0 PRODUCTION 2.03 2021-08-23
xcvc1902 vsva2197 1LP ver_1_vl_64 Variable_Length_Lossless 16 64 CLK 680 48 16 0 0 0 PRODUCTION 2.03 2021-08-23

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_fl_128 Fixed_Length 16 128 CLK 636 64 32 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_fl_512 Fixed_Length 16 512 CLK 636 256 80 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_fl_64 Fixed_Length 16 64 CLK 636 32 32 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_vl_128 Variable_Length_Lossless 16 128 CLK 538 64 16 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_vl_512 Variable_Length_Lossless 16 512 CLK 330 272 16 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_vl_64 Variable_Length_Lossless 16 64 CLK 636 32 16 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_fl_128 Fixed_Length 16 128 CLK 735 64 32 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_fl_512 Fixed_Length 16 512 CLK 735 256 48 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_fl_64 Fixed_Length 16 64 CLK 735 32 32 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_vl_128 Variable_Length_Lossless 16 128 CLK 735 64 16 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_vl_512 Variable_Length_Lossless 16 512 CLK 527 272 16 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_vl_64 Variable_Length_Lossless 16 64 CLK 735 32 16 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_fl_128 Fixed_Length 16 128 CLK 839 64 32 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_fl_512 Fixed_Length 16 512 CLK 872 256 48 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_fl_64 Fixed_Length 16 64 CLK 822 32 32 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_vl_128 Variable_Length_Lossless 16 128 CLK 872 64 16 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_vl_512 Variable_Length_Lossless 16 512 CLK 615 272 16 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 1 vup_1_vl_64 Variable_Length_Lossless 16 64 CLK 872 32 16 0 0 0 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_fl_128 Fixed_Length 16 128 CLK 636 64 32 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_fl_512 Fixed_Length 16 512 CLK 636 256 48 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_fl_64 Fixed_Length 16 64 CLK 636 32 32 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_vl_128 Variable_Length_Lossless 16 128 CLK 636 64 16 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_vl_512 Variable_Length_Lossless 16 512 CLK 511 272 16 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 1LV zup_1_vl_64 Variable_Length_Lossless 16 64 CLK 636 32 16 0 0 0 PRODUCTION 1.29 08-03-2020

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