Performance and Resource Utilization for Reed-Solomon Encoder v9.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 1 k7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 478 198 213 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 275 302 303 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 265 702 491 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 538 174 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 500 284 338 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 424 195 208 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 527 172 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 1 k7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 631 86 105 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 1 ku_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 675 209 215 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 352 316 303 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 341 729 491 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 615 175 181 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 615 332 337 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 593 200 208 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 664 173 182 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 1 ku_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 735 87 105 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 1 kup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 965 204 213 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 472 312 303 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 467 734 491 0 0 1 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 986 175 181 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 330 342 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 866 204 208 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 965 172 184 0 0 0 PRODUCTION 1.29 05-01-2022
xcku11p ffva1156 1 kup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 83 105 0 0 0 PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 664 197 215 0 0 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 604 288 318 0 0 1 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 489 787 671 0 0 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 664 165 184 0 0 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 675 344 355 0 0 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 599 181 217 0 0 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 669 174 181 0 0 0 PRODUCTION 2.12 2023-09-01
xcvc1902 vsva2197 1LP ver_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 680 83 105 0 0 0 PRODUCTION 2.12 2023-09-01

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 1 v7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 505 201 213 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 265 302 303 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 265 707 491 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 538 173 182 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 489 292 336 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 461 198 208 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 522 173 182 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 1 v7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 593 86 105 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 1 vu_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 702 204 215 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 352 300 303 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 341 734 491 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 664 175 182 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 615 331 336 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 566 200 208 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 686 174 181 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 1 vu_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 686 87 105 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 vup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 921 204 215 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 483 309 303 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 467 721 491 0 0 1 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 975 178 185 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 330 337 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 828 204 208 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 981 173 185 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 vup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 85 105 0 0 0 PRODUCTION 1.28 03-30-2022

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 1LV zup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 735 206 214 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 352 299 303 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 363 714 491 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 763 175 182 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 636 331 331 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 636 200 208 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 790 179 185 0 0 0 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 1LV zup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 636 80 105 0 0 0 PRODUCTION 1.30 05-15-2022

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