Performance and Resource Utilization for Reed-Solomon Encoder v9.0

Vivado Design Suite Release 2021.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k70t fbv676 -1 k7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 511 200 213 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 265 301 303 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 265 703 491 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 478 166 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 489 322 337 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 461 199 208 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 511 166 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k70t fbv676 -1 k7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 636 89 105 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku025 ffva1156 -1 ku_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 669 203 213 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 347 310 303 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 341 733 491 0 0 1 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 686 180 185 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 625 333 339 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 625 205 208 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 675 171 181 0 0 0 PRODUCTION 1.25 12-04-2018
xcku025 ffva1156 -1 ku_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 724 89 106 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku11p ffva1156 -1 kup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 965 207 215 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 483 319 303 0 0 1 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 489 735 491 0 0 1 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 997 185 190 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 861 334 339 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 785 199 208 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 992 179 188 0 0 0 PRODUCTION 1.28 02-27-2020
xcku11p ffva1156 -1 kup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 83 105 0 0 0 PRODUCTION 1.28 02-27-2020

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP ver_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 653 205 214 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 461 312 303 0 0 1 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 424 839 499 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 669 174 183 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 647 337 340 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 555 178 208 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 658 177 181 0 0 0 PRODUCTION 2.01 2021-05-28
xcvc1902 vsva2197 1LP ver_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 680 83 107 0 0 0 PRODUCTION 2.01 2021-05-28

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx485t ffg1157 -1 v7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 489 199 213 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 265 302 303 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 254 703 491 0 0 1 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 489 169 181 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 478 316 336 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 402 194 208 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 489 171 181 0 0 0 PRODUCTION 1.12 2014-09-11
xc7vx485t ffg1157 -1 v7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 593 84 105 0 0 0 PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu065 ffvc1517 -1 vu_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 636 204 213 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 352 298 303 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 341 733 491 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 658 183 187 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 625 334 330 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 588 200 209 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 664 172 181 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu065 ffvc1517 -1 vu_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 735 86 105 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 -1 vup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 910 204 213 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 467 316 303 0 0 1 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 467 733 491 0 0 1 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 960 174 181 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 332 337 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 855 204 209 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 927 170 181 0 0 0 PRODUCTION 1.27 02-28-2020
xcvu11p flga2577 -1 vup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 84 105 0 0 0 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1LV zup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 730 205 213 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 358 303 303 0 0 1 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 352 707 491 0 0 1 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 800 181 186 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 636 325 331 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 636 197 208 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 785 173 181 0 0 0 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1LV zup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 636 81 105 0 0 0 PRODUCTION 1.29 08-03-2020

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