Resource Utilization for Serial RapidIO Gen2 v4.1

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2019.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Kintex-7

Part Information			Configuration Parameters									Resource Utilization
Device	Package	Speed Grade	Configuration Name	link_width	transfer_frequency	reference_clock_frequency	idle1_support	idle2_support	silicon_rev	c_support_level	Fixed clocks (MHz)	LUTs	FFs	DSP48s	36k BRAMs	18k BRAMs	BUFGCTRL	BUFR	MMCME2_ADV	Speedfile Status
xc7k325t	ffg900	-2	srio_gen2_conf_1x	1	2.5	125	true	true	Production	Example_Design	drpclk_in=31 gt_clk_in=125 gt_pcs_clk_in=62 log_clk_in=31 phy_clk_in=31 refclk_in=125	6233	7402	0	4	0	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-2	srio_gen2_conf_2x	2	2.5	125	true	true	Production	Example_Design	drpclk_in=62 gt_clk_in=125 gt_pcs_clk_in=62 log_clk_in=62 phy_clk_in=62 refclk_in=125	7669	8246	0	4	0	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k325t	ffg900	-3	srio_gen2_conf_4x	4	2.5	125	true	true	Production	Example_Design	drpclk_in=125 gt_clk_in=125 gt_pcs_clk_in=62 log_clk_in=125 phy_clk_in=125 refclk_in=125	9627	9957	0	4	0	0	0	0	PRODUCTION 1.12 2017-02-17

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