Resource Utilization for System Management Wizard v1.3

Vivado Design Suite Release 2020.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2020.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Kintex UltraScale

Part Information			Configuration Parameters																																																																Resource Utilization
Device	Package	Speed Grade	Configuration Name	INTERFACE_SELECTION	TIMING_MODE	SYSMONE1_STARUP_SELECTION	DCLK_FREQUENCY	ADC_CONVERSION_RATE	SEQUENCER_MODE	ENABLE_CALIBRATION_AVERAGING	ENABLE_CONVST	OT_ALARM	USER_TEMP_ALARM	VCCINT_ALARM	VCCAUX_ALARM	ENABLE_VBRAM_ALARM	TEMPERATURE_ALARM_TRIGGER	TEMPERATURE_ALARM_RESET	TEMPERATURE_ALARM_OT_TRIGGER	TEMPERATURE_ALARM_OT_RESET	VCCINT_ALARM_LOWER	VCCINT_ALARM_UPPER	VCCAUX_ALARM_LOWER	VCCAUX_ALARM_UPPER	VBRAM_ALARM_LOWER	VBRAM_ALARM_UPPER	CHANNEL_AVERAGING	ADC_OFFSET_CALIBRATION	ADC_OFFSET_AND_GAIN_CALIBRATION	SENSOR_OFFSET_CALIBRATION	SENSOR_OFFSET_AND_GAIN_CALIBRATION	ENABLE_EXTERNAL_MUX	EXTERNAL_MUX_CHANNEL	CHANNEL_ENABLE_CALIBRATION	CHANNEL_ENABLE_VCCINT	CHANNEL_ENABLE_VCCAUX	CHANNEL_ENABLE_VP_VN	CHANNEL_ENABLE_VREFP	CHANNEL_ENABLE_VREFN	CHANNEL_ENABLE_VBRAM	AVERAGE_ENABLE_VBRAM	CHANNEL_ENABLE_VAUXP0_VAUXN0	CHANNEL_ENABLE_VAUXP1_VAUXN1	CHANNEL_ENABLE_VAUXP2_VAUXN2	CHANNEL_ENABLE_VAUXP3_VAUXN3	CHANNEL_ENABLE_VAUXP4_VAUXN4	CHANNEL_ENABLE_VAUXP5_VAUXN5	CHANNEL_ENABLE_VAUXP6_VAUXN6	CHANNEL_ENABLE_VAUXP7_VAUXN7	CHANNEL_ENABLE_VAUXP8_VAUXN8	CHANNEL_ENABLE_VAUXP9_VAUXN9	CHANNEL_ENABLE_VAUXP10_VAUXN10	CHANNEL_ENABLE_VAUXP11_VAUXN11	CHANNEL_ENABLE_VAUXP12_VAUXN12	CHANNEL_ENABLE_VAUXP13_VAUXN13	CHANNEL_ENABLE_VAUXP14_VAUXN14	CHANNEL_ENABLE_VAUXP15_VAUXN15	AVERAGE_ENABLE_VP_VN	AVERAGE_ENABLE_VAUXP0_VAUXN0	AVERAGE_ENABLE_VAUXP1_VAUXN1	AVERAGE_ENABLE_VAUXP2_VAUXN2	AVERAGE_ENABLE_VAUXP3_VAUXN3	AVERAGE_ENABLE_VAUXP4_VAUXN4	AVERAGE_ENABLE_VAUXP5_VAUXN5	AVERAGE_ENABLE_VAUXP6_VAUXN6	AVERAGE_ENABLE_VAUXP7_VAUXN7	AVERAGE_ENABLE_VAUXP8_VAUXN8	AVERAGE_ENABLE_VAUXP9_VAUXN9	AVERAGE_ENABLE_VAUXP10_VAUXN10	AVERAGE_ENABLE_VAUXP11_VAUXN11	AVERAGE_ENABLE_VAUXP12_VAUXN12	AVERAGE_ENABLE_VAUXP13_VAUXN13	AVERAGE_ENABLE_VAUXP14_VAUXN14	AVERAGE_ENABLE_VAUXP15_VAUXN15	AVERAGE_ENABLE_TEMPERATURE	AVERAGE_ENABLE_VCCINT	AVERAGE_ENABLE_VCCAUX	BIPOLAR_VP_VN	BIPOLAR_VAUXP0_VAUXN0	BIPOLAR_VAUXP1_VAUXN1	BIPOLAR_VAUXP2_VAUXN2	BIPOLAR_VAUXP3_VAUXN3	BIPOLAR_VAUXP4_VAUXN4	BIPOLAR_VAUXP5_VAUXN5	BIPOLAR_VAUXP6_VAUXN6	BIPOLAR_VAUXP7_VAUXN7	BIPOLAR_VAUXP8_VAUXN8	BIPOLAR_VAUXP9_VAUXN9	BIPOLAR_VAUXP10_VAUXN10	BIPOLAR_VAUXP11_VAUXN11	BIPOLAR_VAUXP12_VAUXN12	BIPOLAR_VAUXP13_VAUXN13	BIPOLAR_VAUXP14_VAUXN14	BIPOLAR_VAUXP15_VAUXN15	ACQUISITION_TIME_VP_VN	ENABLE_JTAG_ARBITER	ACQUISITION_TIME	ENABLE_TEMP_BUS	USER_SUPPLY0_ALARM	USER_SUPPLY1_ALARM	USER_SUPPLY2_ALARM	SELECT_USER_SUPPLY0_LEVEL	SELECT_USER_SUPPLY1_LEVEL	USER_SUPPLY0_ALARM_LOWER	USER_SUPPLY0_ALARM_UPPER	USER_SUPPLY1_ALARM_LOWER	USER_SUPPLY1_ALARM_UPPER	CHANNEL_ENABLE_VUSER0	CHANNEL_ENABLE_VUSER1	CHANNEL_ENABLE_VUSER2	AVERAGE_ENABLE_VUSER0	AVERAGE_ENABLE_VUSER1	AVERAGE_ENABLE_VUSER2	USER_SUPPLY0_BANK	USER_SUPPLY1_BANK	USER_SUPPLY2_BANK	SELECT_USER_SUPPLY0	SELECT_USER_SUPPLY1	SELECT_USER_SUPPLY2	CHANNEL_ENABLE_TEMPERATURE_SLAVE0_SSIT	AVERAGE_ENABLE_TEMPERATURE_SLAVE0_SSIT	ANALOG_BANK_SELECTION	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku060	ffva1517	-2	channel_sequencer_char_conf_1	None	Continuous	channel_sequencer	104	93	Default	true	false	false															None	true	false	true	false			true	true	true				true																																																								true	4																										none	0	0	0	0	0	PRODUCTION 1.25 12-04-2018
xcku040	ffva1156	-2	channel_sequencer_char_conf_3	Enable_DRP	Continuous	channel_sequencer	94	194	One_Pass	true	false	false	true	true	true	true	74	13			0.850000	0.910000	1.750000	1.800000	0.870000	0.930000	None	true	true	false	false	true	VAUXP12_VAUXN12	false	false	false	false	true	true	true	true	false	true	false	false	true	true	true	true	true	true	true	false	true	true	true	true	false	false	true	false	false	false	false	true	true	true	true	true	false	false	true	true	true	true	false	false	false	false	false	false	false	false	true	false	true	true	true	true	false	false	true	true	true	false	true	4		true	false	true	1.2		1.190000	1.260000			true	false	true	false	false	true	48		46	VCCO		VCCINT			48	none	0	0	0	0	0	PRODUCTION 1.25 12-04-2018
xcku115	flva1517	-1	ssit_device_cov_kintex_char_115__conf_1	Enable_AXI	Continuous	channel_sequencer	210	81	One_Pass	true	false	true	false	true	true	true			-34.000000	-39.000000	0.880000	0.930000	1.780000	1.870000	0.870000	0.950000	None	true	true	false	true	false		false	true	true	false	false	true	false	false	true	false	true	false	true	false	false	true	true	true	true	true	true	true	true	false	false	true	false	true	false	false	false	false	false	true	true	true	true	false	true	true	false	false	true	true	false	true	false	false	false	false	false	false	false	false	true	true	true	true	false	true	false	false	false		false	true	true	true		1.2			1.170000	1.200000	false	false	true	false	false	true	24	66	44	VCCAUX	VCCO	VCCINT	false	false	48	s_axi_aclk=210	230	264	0	0	0	PRODUCTION 1.26 12-04-2018

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