Resource Utilization for Video DisplayPort 1.4 TX Subsystem v3.1

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Versal ACAP

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
MODE
PHY_DATA_WIDTH
BITS_PER_COLOR
NUM_STREAMS
LANE_COUNT
AUDIO_ENABLE
Number_of_Audio_Channels
AUX_IO_LOC
AUX_IO_TYPE
HDCP_ENABLE
HDCP22_ENABLE
VIDEO_INTERFACE
PIXEL_MODE
EDP_ENABLE
LINK_RATE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs MMCM BUFGCE URAM Speedfile Status
xcvc1902 vsva2197 3HP versal_default 0 2 8 1 1 0 2 0 0 0 0 0 1 0 8.1 s_axi_aclk=100 s_axis_aclk_stream1=300 tx_enc_clk=405 tx_lnk_clk=506 tx_vid_clk_stream1=300 4708 9327 0 3 1 0 5 0 PRODUCTION 2.12 2023-09-01

Zynq UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
MODE
PHY_DATA_WIDTH
BITS_PER_COLOR
NUM_STREAMS
LANE_COUNT
AUDIO_ENABLE
Number_of_Audio_Channels
AUX_IO_LOC
AUX_IO_TYPE
HDCP_ENABLE
HDCP22_ENABLE
VIDEO_INTERFACE
PIXEL_MODE
EDP_ENABLE
LINK_RATE
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs MMCM PLL BUFGCE Speedfile Status
xczu9eg ffvb1156 2 test_1__tx 0 2 8 1 0 0 0 0 1 s_axi_aclk=100 s_axis_aclk_stream1=300 tx_lnk_clk=405 tx_vid_clk_stream1=300 4538 9267 0 3 1 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_2__tx 0 2 8 4 1 2 0 0 0 4 aud_clk=25 s_axi_aclk=100 s_axis_aclk_stream1=300 s_axis_audio_ingress_aclk=25 tx_lnk_clk=405 tx_vid_clk_stream1=300 9828 14304 0 5 6 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_3__tx 0 2 8 1 1 4 0 1 0 1 aud_clk=25 hdcp_ext_clk=203 s_axi_aclk=100 s_axis_aclk_stream1=300 s_axis_audio_ingress_aclk=25 tx_lnk_clk=405 tx_vid_clk_stream1=300 13997 16637 0 3 2 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_4__tx 0 2 10 4 1 4 0 1 0 4 aud_clk=25 hdcp_ext_clk=203 s_axi_aclk=100 s_axis_aclk_stream1=300 s_axis_audio_ingress_aclk=25 tx_lnk_clk=405 tx_vid_clk_stream1=300 19619 21376 0 7 5 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_5__tx 0 2 16 4 1 4 0 1 1 0 4 aud_clk=25 hdcp_ext_clk=203 s_axi_aclk=100 s_axis_aclk_stream1=300 s_axis_audio_ingress_aclk=25 tx_lnk_clk=405 tx_vid_clk_stream1=300 33526 29700 0 11 5 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_6__tx 0 2 16 1 0 0 1 0 1 hdcp_ext_clk=203 s_axi_aclk=100 s_axis_aclk_stream1=300 tx_lnk_clk=405 tx_vid_clk_stream1=300 12572 14988 0 3 1 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_7__tx 1 2 12 1 1 5 0 0 0 4 aud_clk=25 s_axi_aclk=100 s_axis_aclk_stream1=300 s_axis_aclk_stream2=300 s_axis_audio_ingress_aclk=25 tx_lnk_clk=405 tx_vid_clk_stream1=300 tx_vid_clk_stream2=300 17738 23520 0 16 11 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_8__tx 1 2 16 2 1 2 0 0 1 4 aud_clk=25 s_axi_aclk=100 s_axis_audio_ingress_aclk=25 tx_lnk_clk=405 tx_vid_clk_stream1=300 tx_vid_clk_stream2=300 14918 16210 0 0 9 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 2 test_9__tx 1 2 10 4 0 0 0 1 4 s_axi_aclk=100 tx_lnk_clk=405 tx_vid_clk_stream1=300 tx_vid_clk_stream2=300 11592 13732 0 0 8 0 0 1 PRODUCTION 1.30 05-15-2022
xczu9eg ffvb1156 3 uplus_default 0 2 8 1 1 0 2 0 0 0 0 0 1 0 8.1 s_axi_aclk=100 s_axis_aclk_stream1=300 tx_lnk_clk=405 tx_vid_clk_stream1=300 4536 9268 0 3 1 0 0 1 PRODUCTION 1.30 05-15-2022

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