Performance and Resource Utilization for Gamma LUT v1.1

Vivado Design Suite Release 2024.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Artix-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7a200t ffg1156 2 v_gamma_char__conf_07 8 3840 2160 8 ap_clk 232 1362 1937 0 9 24 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 2 v_gamma_char__conf_08 8 3840 2160 10 ap_clk 232 1587 2373 0 9 26 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 2 v_gamma_char__conf_10 1 3840 2160 10 ap_clk 250 661 897 0 3 3 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 2 v_gamma_char__conf_11 2 3840 2160 8 ap_clk 269 776 1116 0 3 6 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 2 v_gamma_char__conf_17 1 3840 2160 8 ap_clk 241 626 768 0 3 3 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 2 v_gamma_char__conf_19 2 3840 2160 8 ap_clk 269 776 1116 0 3 6 PRODUCTION 1.23 2018-06-13
xc7a200t ffg1156 2 v_gamma_char__conf_21 4 3840 2160 8 ap_clk 250 972 1464 0 5 14 PRODUCTION 1.23 2018-06-13

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t ffg900 2 v_gamma_char__conf_01 1 3840 2160 8 ap_clk 400 1040 1009 0 0 3 PRODUCTION 1.12 2017-02-17
xc7k325t ffg900 2 v_gamma_char__conf_23 8 3840 2160 8 ap_clk 373 1874 2527 0 4 24 PRODUCTION 1.12 2017-02-17

Versal ACAP

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
Clock Input Fmax (MHz) LUTs FFs DSPs Ultra RAMs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 1LP v_gamma_char__conf_02 1 3840 2160 10 ap_clk 485 760 986 0 0 3 3 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 2MP v_gamma_char__conf_03 2 3840 2160 8 ap_clk 644 1066 1261 0 0 3 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP v_gamma_char__conf_04 2 3840 2160 10 ap_clk 448 908 1305 0 0 3 6 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP v_gamma_char__conf_05 4 3840 2160 8 ap_clk 466 2043 2115 0 0 1 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 2MP v_gamma_char__conf_06 4 3840 2160 10 ap_clk 635 1373 2117 0 0 3 12 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP v_gamma_char__conf_12 2 3840 2160 10 ap_clk 448 908 1305 0 0 3 6 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 2MP v_gamma_char__conf_13 4 3840 2160 8 ap_clk 663 1732 2328 0 0 3 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP v_gamma_char__conf_14 4 3840 2160 10 ap_clk 438 1274 2091 0 0 3 12 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 2MP v_gamma_char__conf_15 8 3840 2160 8 ap_clk 625 2792 3376 0 0 3 0 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 2MP v_gamma_char__conf_16 8 3840 2160 10 ap_clk 635 2005 3233 0 0 3 24 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 2MP v_gamma_char__conf_20 2 3840 2160 10 ap_clk 654 940 1328 0 0 3 6 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP v_gamma_char__conf_22 4 3840 2160 10 ap_clk 438 1274 2091 0 0 3 12 PRODUCTION 2.13 2024-03-28
xcvc1902 vsva2197 1LP v_gamma_char__conf_24 8 3840 2160 10 ap_clk 466 2163 3746 0 0 3 24 PRODUCTION 2.13 2024-03-28

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu7ev ffvc1156 2 v_gamma_char__conf_09 1 3840 2160 8 ap_clk 616 742 785 0 3 0 PRODUCTION 1.30 05-15-2022
xczu7ev ffvc1156 2 v_gamma_char__conf_18 1 3840 2160 10 ap_clk 616 678 791 0 3 3 PRODUCTION 1.30 05-15-2022

COPYRIGHT

Copyright 2024 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.