Resource Utilization for SMPTE UHD-SDI v1.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
The frequencies used for clock inputs are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Virtex-7

Part Information			Configuration Parameters				Resource Utilization
Device	Package	Speed Grade	Configuration Name	INCLUDE_RX_EDH_PROCESSOR	LINE_RATE	Fixed clocks (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_12g_16ds_1	FALSE	12G_SDI_16DS	rx_clk=297 tx_clk=297	4648	6708	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_12g_16ds_edh_1	TRUE	12G_SDI_16DS	rx_clk=297 tx_clk=297	5040	7144	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_12g_8ds_1	FALSE	12G_SDI_8DS	rx_clk=297 tx_clk=297	3511	4800	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_12g_8ds_edh_1	TRUE	12G_SDI_8DS	rx_clk=297 tx_clk=297	3900	5235	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_3g_1	FALSE	3G_SDI	rx_clk=148 tx_clk=148	2414	2927	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_3g_edh_1	TRUE	3G_SDI	rx_clk=148 tx_clk=148	2766	3361	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_6g_1	FALSE	6G_SDI	rx_clk=148 tx_clk=148	3356	4792	0	0	0	PRODUCTION 1.11 2014-09-11
xc7vx690t	ffg1930	3	test_smpte_uhdsdi_6g_edh_1	TRUE	6G_SDI	rx_clk=148 tx_clk=148	3733	5226	0	0	0	PRODUCTION 1.11 2014-09-11

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