Performance and Resource Utilization for Video Timing Controller v6.2

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

Artix-7
artixuplus
Kintex-7
Kintex UltraScale
Kintex UltraScale+
Versal ACAP
Virtex-7
Virtex UltraScale
Virtex UltraScale+
Zynq-7000
Zynq UltraScale+

Artix-7

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7a200t	sbv484	3	artix7_det_gen_waxi_wint_19	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	286	1952	3752	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a200t	sbg484	2	artix7_det_waxi_wint_18	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	265	1492	3111	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a100t	csg324	3	artix7_det_woaxi_wint_17	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	330	300	695	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a100t	csg324	1	artix7_gen_waxi_16	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	221	1033	2793	0	0	0	PRODUCTION 1.23 2018-06-13
xc7a75t	csg324	3	artix7_gen_woaxi_15	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	330	98	131	0	0	0	PRODUCTION 1.23 2018-06-13

artixuplus

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcau25p	ffvb676	1	artixup_det_gen_waxi_wint_24	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	607	2128	3770	0	0	0	PRODUCTION 1.29 05-01-2022
xcau25p	ffvb676	1LV	artixup_det_waxi_wint_23	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	465	1524	3125	0	0	0	PRODUCTION 1.29 05-01-2022
xcau25p	ffvb676	2	artixup_det_woaxi_wint_22	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	777	378	697	0	0	0	PRODUCTION 1.29 05-01-2022
xcau20p	ffvb676	2	artixup_gen_waxi_21	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	799	1054	2800	0	0	0	PRODUCTION 1.29 05-01-2022
xcau20p	ffvb676	1	artixup_gen_woaxi_20	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	880	104	131	0	0	0	PRODUCTION 1.29 05-01-2022

Kintex-7

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7k70t	fbv676	3	kintex7_det_gen_waxi_wint_4	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	429	1978	3753	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbg676	2	kintex7_det_waxi_wint_3	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	418	1493	3110	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	3	kintex7_det_woaxi_wint_2	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	467	351	695	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	2	kintex7_gen_waxi_1	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	429	1053	2793	0	0	0	PRODUCTION 1.12 2017-02-17
xc7k70t	fbv676	1	kintex7_gen_woaxi_0	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	385	100	131	0	0	0	PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku040	ffva1156	3	kintexu_det_gen_waxi_wint_9	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	543	2131	3778	0	0	0	PRODUCTION 1.25 12-04-2018
xcku035	fbva676	2	kintexu_det_waxi_wint_8	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	519	1558	3124	0	0	0	PRODUCTION 1.25 12-04-2018
xcku035	fbva676	2	kintexu_det_woaxi_wint_7	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	613	372	697	0	0	0	PRODUCTION 1.25 12-04-2018
xcku025	ffva1156	1	kintexu_gen_waxi_6	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	519	1054	2803	0	0	0	PRODUCTION 1.25 12-04-2018
xcku035	fbva676	3	kintexu_gen_woaxi_5	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	825	103	138	0	0	0	PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcku15p	ffva1156	3	kintexup_det_gen_waxi_wint_14	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	755	2155	3800	0	0	0	PRODUCTION 1.29 05-01-2022
xcku15p	ffva1156	2L	kintexup_det_waxi_wint_13	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	711	1590	3120	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	3	kintexup_det_woaxi_wint_12	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	815	373	695	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	2	kintexup_gen_waxi_11	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	815	1057	2804	0	0	0	PRODUCTION 1.29 05-01-2022
xcku11p	ffva1156	1	kintexup_gen_woaxi_10	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	733	96	131	0	0	0	PRODUCTION 1.29 05-01-2022

Versal ACAP

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsvd1760	2MP	versal_det_gen_waxi_wint_54	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	644	2379	3710	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	2MP	versal_det_waxi_wint_53	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	675	1891	3074	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	2MP	versal_det_woaxi_wint_52	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	723	514	703	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	3HP	versal_gen_waxi_51	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	810	1160	2803	0	0	0	PRODUCTION 2.12 2023-09-01
xcvc1902	vsva2197	1LP	versal_gen_woaxi_50	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	621	180	151	0	0	0	PRODUCTION 2.12 2023-09-01

Virtex-7

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7vx485t	ffg1157	1	virtex7_det_gen_waxi_wint_29	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	319	1969	3752	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	virtex7_det_waxi_wint_28	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	341	1507	3111	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	virtex7_det_woaxi_wint_27	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	385	302	696	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	3	virtex7_gen_waxi_26	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	440	1052	2793	0	0	0	PRODUCTION 1.12 2014-09-11
xc7vx485t	ffg1157	1	virtex7_gen_woaxi_25	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	391	98	131	0	0	0	PRODUCTION 1.12 2014-09-11

Virtex UltraScale

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu065	ffvc1517	3	virtexu_det_gen_waxi_wint_34	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	550	2130	3785	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	3	virtexu_det_waxi_wint_33	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	566	1574	3120	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	2	virtexu_det_woaxi_wint_32	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	590	373	695	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	2	virtexu_gen_waxi_31	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	582	1060	2803	0	0	0	PRODUCTION 1.27 12-04-2018
xcvu065	ffvc1517	1	virtexu_gen_woaxi_30	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	613	104	142	0	0	0	PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvu11p	flga2577	3	virtexup_det_gen_waxi_wint_39	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	804	2136	3782	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	3	virtexup_det_waxi_wint_38	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	804	1581	3134	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	2	virtexup_det_woaxi_wint_37	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	788	369	695	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	virtexup_gen_waxi_36	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	694	1055	2800	0	0	0	PRODUCTION 1.28 03-30-2022
xcvu11p	flga2577	1	virtexup_gen_woaxi_35	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	799	103	132	0	0	0	PRODUCTION 1.28 03-30-2022

Zynq-7000

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xc7z010	clg225	3	zynq_det_gen_waxi_wint_44	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	275	1952	3752	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z007s	clg400	2	zynq_det_waxi_wint_43	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	260	1486	3112	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z010	clg400	3	zynq_det_woaxi_wint_42	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	325	300	695	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z010	clg400	2	zynq_gen_waxi_41	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	275	1034	2793	0	0	0	PRODUCTION 1.12 2019-11-22
xc7z010	clg400	1	zynq_gen_woaxi_40	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	243	98	131	0	0	0	PRODUCTION 1.12 2019-11-22

Zynq UltraScale+

Part Information			Configuration Parameters																					Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	HAS_AXI4_LITE	INTERLACE_EN	max_clocks_per_line	max_lines_per_frame	VIDEO_MODE	horizontal_sync_generation	enable_detection	vertical_blank_generation	GEN_FIELDID_EN	horizontal_blank_detection	horizontal_sync_detection	enable_generation	vertical_sync_generation	DET_FIELDID_EN	vertical_blank_detection	active_video_generation	vertical_sync_detection	horizontal_blank_generation	active_video_detection	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu28dr	fsvg1517	2	zynqup_det_gen_waxi_wint_49	true	true	4096	4096	Custom	true	true	true	true	true	true	true	true	true	true		true	true	true	s_axi_aclk=100	clk	694	2137	3789	0	0	0	PRODUCTION 1.30 05-03-2022
xczu28dr	fsvg1517	2	zynqup_det_waxi_wint_48	true	true	4096	4096	Custom		true			true	true	false		true	true		true		true	s_axi_aclk=100	clk	705	1585	3141	0	0	0	PRODUCTION 1.30 05-03-2022
xczu28dr	fsvg1517	1	zynqup_det_woaxi_wint_47	false	true	4096	4096	Custom		true			true	true	false		true	true		true		true	none	clk	635	368	695	0	0	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	2	zynqup_gen_waxi_46	true	true	4096	4096	Custom	true	false	true	true			true	true			true		true		s_axi_aclk=100	clk	793	1056	2803	0	0	0	PRODUCTION 1.30 05-03-2022
xczu21dr	ffvd1156	1	zynqup_gen_woaxi_45	false	true	4096	4096	Custom	true	false	true	true			true	true			true		true		none	clk	797	97	131	0	0	0	PRODUCTION 1.30 05-03-2022

COPYRIGHT

Copyright 2023 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.