Creating the Hardware Component

Begin by setting up the Vitis integrated design environment (IDE) by sourcing the Vitis setup script (*.sh,*.csh) consistent with the type of target platform (bash, csh) running in your terminal window. The Vivado Design Suite is included with the Vitis IDE. For developers that just have a Vivado installation, Vitis can be used to create the hardware component as described below, but the Vitis IDE will be necessary for creating the Vitis target platforms.

source <Vitis_Install_Directory>/settings64.sh or
       <Vivado_Install_Directory>/settings64.sh

The Vitis GUI presents a series of dialog boxes to guide you through creating a project for hardware development. Use the following instructions to answer the sequence of Vitis dialog boxes in creating the project and then continue by creating a Vitis IP integrator block design as the base hardware for the Vitis target platform. The hardware requirements for a design that supports acceleration kernels is provided in Hardware Component Requirements.

  1. Create a working directory by using the naming convention <platform_name>_pkg and generate a Vivado sub-directory to launch the Vivado Design Suite:
    1. mkdir zcu102_min_pkg
    2. cd zcu102_min_pkg
    3. mkdir vivado
    4. cd vivado
    5. vivado
  2. Create a new project using the Vivado menu or the quick start link on the Welcome page.
    1. Select File > Project > New.
    2. Click Next.
  3. In the Project Name dialog:
    1. Set the Project Name. In this example, it is set to the default name of project_1.
    2. Keep the default project directory. If desired, select the ellipsis button to navigate to a different location.
    3. Retain the default Create project sub-directory check marked.
    4. Click Next.
  4. In the Project Type dialog:
    1. Keep default of RTL Project selected.
    2. Leave the following default not selected:
      • Post-synthesis Project
      • I/O Planning Project
      • Imported Project
      • Example Project
    3. Click Next.
  5. In the Add Sources dialog, do not add sources.
    1. Keep default Target language as Verilog.
    2. Keep default Simulator language as Mixed.
    3. Click Next.
  6. In the Add Constraints dialog, do not add constraints. Click Next.
  7. In the Default Part dialog, select the ZCU102 board.
    1. On the Parts | Boards selection, click Boards.
    2. On the Filter Search text box, enter zcu102.
    3. Select the ZCU102 board shown in the board listing.
    4. Click Next.
  8. In the New Project Summary dialog:
    1. Check the settings and click Back, if needed.
    2. Click Finish to create the Vivado project.

Use the IP integrator to create a block design and generate a Xilinx Shell Archive (XSA). The XSA contains the hardware specification and metadata for constructing the Vitis target platform. Begin by creating a block design with the IP integrator.

  1. In the Vivado Flow Navigator, click IP Integrator > Create Block Design.
  2. In the Create Block Design dialog:
    1. Keep the default Design name as design_1.
    2. Keep the default Directory of <Local to Project>.
    3. Leave the default Specify source set as Design Sources.
    4. Click OK.
  3. In the block diagram view:
    1. Click the + button to add instances of new IP. The search dialog can be used to find the desired IP blocks.
    2. Search for zynq.
    3. Select Zynq UltraScale+ MPSoC from the IP search results.

A Zynq UltraScale+ MPSoC block is added to the IP integrator diagram and can be customized. Because the selected default was a board, ZCU102, there are board presets available for customizing this IP block.

  1. Click the Run Block Automation link to apply the board presets.
  2. In the Run Block Automation dialog, ensure the following is check marked:
    • All Automation
    • Zynq_ultra_ps_e_0
    • Apply Board Presets
  3. Click OK.

The next phase is deciding if the base hardware design will be used similarly as a pre-2019.2 SDK software flow or attaching hardware accelerators, known as kernels, to extend its design capabilities. To generate an XSA that is used like an HDF, similar to the SDK tools, see XSA for Embedded Software Development. To create an XSA that supports the addition of acceleration kernels, see XSA for Application Acceleration Development Flow.

XSA for Embedded Software Development

For maintaining continuity with the SDK development flow, complete the hardware design process in Vivado and export a hardware specification to feed into downstream tools, just as was done in prior releases. Instead of an HDF formatted hardware specification, the Vivado export will now output an XSA formatted hardware specification. This XSA file can be used in the Vitis IDE to create a target platform with a standalone domain to begin standalone or baremetal software development. For Linux application development, the XSA hardware specification is an input to the PetaLinux tool flow for creating a set of Linux software image and object files along with a root file system. The PetaLinux generated files are then used in constructing a Vitis target platform that includes a Linux domain.

Generating a Hardware Design for Embedded Software Development

To generate an SDK flow type of hardware design, follow the steps below. To create a hardware design compatible with applications that use kernels, skip the following steps and see XSA for Application Acceleration Development Flow.

At this stage, the Vivado block automation has added a Zynq UltraScale+ MPSoC block and applied all board presets for the ZCU102. Wire the clock signals for the HPM interfaces and validate the IP integrator design before generating the output products, a bitstream, and exporting the hardware. The IP integrator block diagram in this example is shown below for generating an XSA that supports an SDK flow. Additional PL logic or different PS customization settings can be applied before exporting the hardware to generate the XSA.

  1. Connect pl_clk0 to maxihpm0_fpd_aclk and maxihpm1_fpd_aclk.
  2. Validate the design by clicking the box with a check mark icon on the IP integrator icon menu.

  3. In the Sources view, right-click BD design (design_1.bd) and select Generate Output Products.
    1. Use default settings for Synthesis Options: Out-of-context per IP.
    2. Use default settings for Run Settings: On local host.
    3. Click Generate.
    4. On the Design Runs tab, expand the Out-of-Context Module Runs and observe a green check mark next to the design name when generation is complete.
  4. In the Sources view, right-click BD design and select Create HDL Wrapper.
    1. Use default options settings: Let Vivado manage wrapper and auto-update.
    2. Click OK.
  5. In the Flow Navigator, select Program and Debug > Generate Bitstream.
    1. Click Yes to launch synthesis and implementation.
    2. Use defaults on the Launch Runs dialog and click OK.
    3. Observe Bitstream Generation Completed message, click Cancel to continue.
  6. Export the hardware design by selecting File > Export > Export Hardware.
    1. Click Include bitstream.
    2. Leave defaults for other settings.
    3. Click OK.
  7. Observe that an XSA (design_1_wrapper.xsa) has been generated and placed in the Vivado project directory.

You have finished creating the XSA containing the hardware specification for use with the Vitis embedded software development flow. A Vitis software application can be created using this XSA like the method; this is similar to how an exported HDF was used to develop SDK software applications in the pre-2019.2 tools. If this XSA will be used for a Linux application, continue with Creating the Software Component, otherwise go to Creating the Platform.

XSA for Application Acceleration Development Flow

At this stage, the Vivado block automation has added a Zynq UltraScale+ MPSoC block and applied all board presets for the ZCU102. Add the IP blocks and metadata to create a base hardware design that supports acceleration kernels.

Re-Customizing the Processor IP Block

Before adding the IP, re-customize the processor IP block using the following steps. The resulting block diagram is shown in the following figure.

  1. Double-click the Zynq UltraScale+ MPSoC block in the IP integrator diagram.
  2. Select Page Navigator > PS-PL Configuration.
  3. Expand PS-PL Configuration > PS-PL Interfaces by clicking the > symbol.
  4. Expand the Master interface configuration.
  5. Uncheck the AXI HMP0 FPD and AXI HPM1 FPD interfaces.
  6. Click OK.
  7. Confirm that the IP block interfaces were removed.

Adding IP Blocks

Add IP blocks to meet the hardware requirements for supporting kernels in an embedded system as described below. On the IP integrator block diagram, IP is added by clicking the + icon and entering the name of the block in the Search dialog. The resulting block diagram is shown below.

  1. Add a clocking wizard IP block by double-clicking its name in the IP Search dialog.
  2. Customize the clocking wizard to generate five (5) output clocks by double-clicking the clk_wiz_0 IP block.
  3. Click the Output Clocks tab.
  4. Add five clocks (clk_out1 to clk_out5) by clicking the box in the Output Clock column.
  5. Set the frequencies as listed:
    1. clk_out1 to 100 MHz.
    2. clk_out2 to 200 MHz.
    3. clk_out3 to 300 MHz.
    4. clk_out4 to 400 MHz.
    5. clk_out5 to 500 MHz.
  6. Set the Reset Type to Active-Low.
  7. Add five (5) processor system reset IP blocks. Copy (Ctrl-C) and Paste (Ctrl-V) operations can be performed on the IP blocks.
  8. Click Run Connection Automation to streamline connecting and associating a processor system reset block with each clock output of the clocking wizard.
  9. Select the slowest_sync_clk choice on each proc_sys_reset instance listed and use the Clock source pull-down menu to make the following associations:
    1. proc_sys_reset_0 with /clk_wiz_0/clk_out1.
    2. proc_sys_reset_1 with /clk_wiz_0/clk_out2.
    3. proc_sys_reset_2 with /clk_wiz_0/clk_out3.
    4. proc_sys_reset_3 with /clk_wiz_0/clk_out4.
    5. proc_sys_reset_4 with /clk_wiz_0/clk_out5.
  10. Select the clk_in1 choice for the clk_wiz_0 instance and make the association:
    1. clk_wiz_0 with /zynq_ultra_ps_e_0/pl_clk0.
    2. Click OK.
  11. Connect all the resets:
    1. /proc_sys_reset0/ext_reset_in to /zynq_ultra_ps_e_0/pl_resetn0.
    2. /proc_sys_reset1/ext_reset_in to /zynq_ultra_ps_e_0/pl_resetn0.
    3. /proc_sys_reset2/ext_reset_in to /zynq_ultra_ps_e_0/pl_resetn0.
    4. /proc_sys_reset3/ext_reset_in to /zynq_ultra_ps_e_0/pl_resetn0.
    5. /proc_sys_reset4/ext_reset_in to /zynq_ultra_ps_e_0/pl_resetn0.
    6. /clk_wiz_0/reset_n to /zynq_ultra_ps_e_0/pl_resetn0.
  12. Connect all the dcm_locked signals:
    1. /proc_sys_reset0/dcm_locked to /clk_wiz_0/locked.
    2. /proc_sys_reset1/dcm_locked to /clk_wiz_0/locked.
    3. /proc_sys_reset2/dcm_locked to /clk_wiz_0/locked.
    4. /proc_sys_reset3/dcm_locked to /clk_wiz_0/locked.
    5. /proc_sys_reset4/dcm_locked to /clk_wiz_0/locked.
After completing the steps above, the hardware design diagram should look like the figure below. Add the target platform properties and declare interfaces available to the v++ linker for integrating kernels with the base hardware design.

Declaring Platform (PFM) Interfaces and Properties

The method to declare the PFM interfaces and properties is through the Platform Interfaces view of the IP integrator block design. Enable the Platform interfaces view by selecting Window > Platform Interfaces on the Vivado menu bar and then click the Enable platform interfaces link. The Platform view displays the IP blocks in the design. By following the steps below, interfaces are declared as enabled or disabled for use by the v++ linker when it integrates kernels into the hardware design. The Ctrl or Shift keys can be used to set multiple interfaces simultaneously.Configuring Platform Interface Properties describes how to set the platform properties with the Tcl commands.

  1. Expand the zynq_ultra_ps_e_0 block shown in the Platform interfaces view.
  2. Enable the interfaces by right-clicking an interface and selecting Enable to the following:
    1. Enable M_AXI_HPM0_FPD.
    2. Enable M_AXI_HPM1_FPD.
    3. Enable M_AXI_HPM0_LPD.
    4. Enable S_AXI_HPC0_FPD.
    5. Enable S_AXI_HPC1_FPD.
    6. Enable S_HP0_FPD.
    7. Enable S_HP1_FPD.
    8. Enable S_HP2_FPD.
    9. Enable S_HP3_FPD.
  3. Disable the interfaces by right-clicking an interface and selecting Disable to the following:
    1. Disable S_AXI_LPD.
    2. Disable pl_clk0.
    3. Disable S_AXI_ACP_FPD.
  4. Expand the clk_wiz_0 block and enable all clocks, clk_out1 through clk_out5.
  5. Select clk_out3 and edit its Platform Interface Properties in the Options view.
    1. Set id = 0.
      Note: You must click Enter to finalize changes after edits.
    2. Select is_default by clicking the box.
    3. Ensure status = fixed.
  6. Expand the xlconcat_0 block and enable In0 through In7.

Project properties are also set to inform downstream tools of the intended use of the target platform's hardware design, before running the implementation tools and generating a bitstream.

  1. Set the project design intent and output type properties by using the Tcl console to enter the commands shown:
    set_property platform.design_intent.embedded true [current_project]
    set_property platform.design_intent.server_managed false [current_project]
    set_property platform.design_intent.external_host false [current_project]
    set_property platform.design_intent.datacenter false [current_project]
    set_property platform.default_output_type "sd_card" [current_project]
    
  2. Validate the block design by right-clicking the IP integrator canvas and selecting Validate Design.
  3. In the Sources view, right-click BD design (design_1.bd) and select Generate Output Products.
    1. Use default settings for Synthesis Options: Out-of-context per IP.
    2. Use default settings for Run Settings: On local host.
    3. Click Generate.
    4. On the Design Runs tab, expand the Out-of-Context Module Runs and observe a green check mark next to the design name when generation is complete.
  4. In the Sources view, right-click BD design and select Create HDL Wrapper.
    1. Use default options settings: Let Vivado manage wrapper and auto-update.
    2. Click OK.
  5. In the Flow Navigator, select Program and Debug > Generate Bitstream.
    1. Click Yes to launch synthesis and implementation.
    2. Use defaults on the Launch Runs dialog and click OK.
    3. Observe Bitstream Generation Completed message, click Cancel to continue.
  6. Create the XSA with the following Tcl command:
    write_hw_platform -include_bit zcu102_min.xsa
  7. Validate the XSA:
    validate_hw_platform ./zcu102_min.xsa
  8. Observe that an XSA (zcu102_min.xsa) has been generated and placed at the same level as the Vivado project directory.

An XSA with kernel support has now been created and can be used as the hardware component in a Vitis target platform project to provide kernel-based application acceleration. The target platform also requires a software component. The PetaLinux tools are used to generate the Linux software components and include the XRT library support with the additions shown in Creating the Software Component.