This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.
Data is provided for the following device families:
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xc7a200t | fbg484 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=538 | *ACLK | 538 | 155 | 300 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7a200t | fbg484 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=494 | *ACLK | 494 | 156 | 302 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7a200t | fbg484 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=391 | *ACLK | 391 | 152 | 391 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7a200t | fbg484 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=297 inst/M01_AXIS_ACLK=297 inst/M02_AXIS_ACLK=297 inst/M03_AXIS_ACLK=297 | *ACLK | 297 | 1323 | 4492 | 0 | 8 | 1 | PRODUCTION 1.23 2018-06-13 | ||||
xc7a200t | fbg484 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=435 inst/S00_AXIS_ACLK=435 | *ACLK | 435 | 136 | 332 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||
xc7a200t | fbg484 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=336 inst/S00_AXIS_ACLK=336 | *ACLK | 336 | 54 | 210 | 0 | 2 | 1 | PRODUCTION 1.23 2018-06-13 | |||||||||||
xc7a200t | fbg484 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=330 inst/S00_AXIS_ACLK=330 | *ACLK | 330 | 64 | 220 | 0 | 2 | 1 | PRODUCTION 1.23 2018-06-13 | |||||||||||
xc7a200t | fbg484 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=489 inst/S00_AXIS_ACLK=489 | *ACLK | 489 | 22 | 196 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7a200t | fbg484 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=461 inst/S00_AXIS_ACLK=461 | *ACLK | 461 | 94 | 193 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7a200t | fbg484 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=440 inst/S00_AXIS_ACLK=440 | *ACLK | 440 | 23 | 735 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7a200t | fbg484 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=424 inst/S00_AXIS_ACLK=424 | *ACLK | 424 | 316 | 733 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7a200t | fbg484 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=472 inst/S00_AXIS_ACLK=472 | *ACLK | 472 | 46 | 83 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7a200t | fbg484 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=483 inst/S00_AXIS_ACLK=483 | *ACLK | 483 | 156 | 299 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7a200t | fbg484 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=402 inst/S00_AXIS_ACLK=402 | *ACLK | 402 | 588 | 1164 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7a200t | fbg484 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=407 inst/M01_AXIS_ACLK=407 inst/S00_AXIS_ACLK=407 | *ACLK | 407 | 169 | 310 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||
xc7a200t | fbg484 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=407 inst/M01_AXIS_ACLK=407 inst/M02_AXIS_ACLK=407 inst/M03_AXIS_ACLK=407 inst/S00_AXIS_ACLK=407 | *ACLK | 407 | 74 | 100 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7a200t | fbg484 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=341 inst/M01_AXIS_ACLK=341 inst/M02_AXIS_ACLK=341 inst/M03_AXIS_ACLK=341 inst/S00_AXIS_ACLK=341 | *ACLK | 341 | 183 | 316 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7a200t | fbg484 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=330 inst/M01_AXIS_ACLK=330 inst/M02_AXIS_ACLK=330 inst/M03_AXIS_ACLK=330 inst/S00_AXIS_ACLK=330 | *ACLK | 330 | 328 | 1181 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7a200t | fbg484 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=358 inst/S00_AXIS_ACLK=358 inst/S01_AXIS_ACLK=358 | *ACLK | 358 | 424 | 626 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||
xc7a200t | fbg484 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=325 inst/M01_AXIS_ACLK=325 inst/S00_AXIS_ACLK=325 inst/S01_AXIS_ACLK=325 | *ACLK | 325 | 382 | 641 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||
xc7a200t | fbg484 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=319 inst/S00_AXIS_ACLK=319 inst/S01_AXIS_ACLK=319 inst/S02_AXIS_ACLK=319 inst/S03_AXIS_ACLK=319 | *ACLK | 319 | 316 | 390 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7a200t | fbg484 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=297 inst/S00_AXIS_ACLK=297 inst/S01_AXIS_ACLK=297 inst/S02_AXIS_ACLK=297 inst/S03_AXIS_ACLK=297 | *ACLK | 297 | 987 | 1254 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7a200t | fbg484 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=275 inst/S00_AXIS_ACLK=275 inst/S01_AXIS_ACLK=275 inst/S02_AXIS_ACLK=275 inst/S03_AXIS_ACLK=275 | *ACLK | 275 | 1862 | 4716 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7a200t | fbg484 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=297 inst/M01_AXIS_ACLK=297 inst/M02_AXIS_ACLK=297 inst/M03_AXIS_ACLK=297 inst/S00_AXIS_ACLK=297 inst/S01_AXIS_ACLK=297 inst/S02_AXIS_ACLK=297 inst/S03_AXIS_ACLK=297 | *ACLK | 297 | 512 | 497 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||
xc7a200t | fbg484 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=265 inst/M01_AXIS_ACLK=265 inst/M02_AXIS_ACLK=265 inst/M03_AXIS_ACLK=265 inst/S00_AXIS_ACLK=265 inst/S01_AXIS_ACLK=265 inst/S02_AXIS_ACLK=265 inst/S03_AXIS_ACLK=265 | *ACLK | 265 | 1140 | 1361 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||
xc7a200t | fbg484 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=249 inst/M01_AXIS_ACLK=249 inst/M02_AXIS_ACLK=249 inst/M03_AXIS_ACLK=249 inst/S00_AXIS_ACLK=249 inst/S01_AXIS_ACLK=249 inst/S02_AXIS_ACLK=249 inst/S03_AXIS_ACLK=249 | *ACLK | 249 | 6051 | 4817 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xc7k480t | ffg901 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=615 | *ACLK | 615 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||||
xc7k480t | ffg901 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=577 | *ACLK | 577 | 155 | 301 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||||
xc7k480t | ffg901 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=577 | *ACLK | 577 | 154 | 391 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||||
xc7k480t | ffg901 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=396 inst/M01_AXIS_ACLK=396 inst/M02_AXIS_ACLK=396 inst/M03_AXIS_ACLK=396 | *ACLK | 396 | 1609 | 4484 | 0 | 8 | 1 | PRODUCTION 1.12 2017-02-17 | ||||
xc7k480t | ffg901 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=647 inst/S00_AXIS_ACLK=647 | *ACLK | 647 | 139 | 332 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||||||||
xc7k480t | ffg901 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=467 inst/S00_AXIS_ACLK=467 | *ACLK | 467 | 55 | 65 | 0 | 2 | 1 | PRODUCTION 1.12 2017-02-17 | |||||||||||
xc7k480t | ffg901 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=472 inst/S00_AXIS_ACLK=472 | *ACLK | 472 | 72 | 75 | 0 | 2 | 1 | PRODUCTION 1.12 2017-02-17 | |||||||||||
xc7k480t | ffg901 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=724 inst/S00_AXIS_ACLK=724 | *ACLK | 724 | 25 | 195 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||||||||||
xc7k480t | ffg901 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=686 inst/S00_AXIS_ACLK=686 | *ACLK | 686 | 95 | 193 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||||||||||
xc7k480t | ffg901 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=642 inst/S00_AXIS_ACLK=642 | *ACLK | 642 | 23 | 735 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||||||||||
xc7k480t | ffg901 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=631 inst/S00_AXIS_ACLK=631 | *ACLK | 631 | 317 | 733 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||||||||||
xc7k480t | ffg901 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=774 inst/S00_AXIS_ACLK=774 | *ACLK | 774 | 48 | 83 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||||
xc7k480t | ffg901 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=708 inst/S00_AXIS_ACLK=708 | *ACLK | 708 | 156 | 299 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||||
xc7k480t | ffg901 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=593 inst/S00_AXIS_ACLK=593 | *ACLK | 593 | 588 | 1164 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||||
xc7k480t | ffg901 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=582 inst/M01_AXIS_ACLK=582 inst/S00_AXIS_ACLK=582 | *ACLK | 582 | 171 | 310 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||
xc7k480t | ffg901 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=566 inst/M01_AXIS_ACLK=566 inst/M02_AXIS_ACLK=566 inst/M03_AXIS_ACLK=566 inst/S00_AXIS_ACLK=566 | *ACLK | 566 | 73 | 100 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||
xc7k480t | ffg901 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=527 inst/M01_AXIS_ACLK=527 inst/M02_AXIS_ACLK=527 inst/M03_AXIS_ACLK=527 inst/S00_AXIS_ACLK=527 | *ACLK | 527 | 184 | 316 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||
xc7k480t | ffg901 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=461 inst/M01_AXIS_ACLK=461 inst/M02_AXIS_ACLK=461 inst/M03_AXIS_ACLK=461 inst/S00_AXIS_ACLK=461 | *ACLK | 461 | 616 | 1181 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||
xc7k480t | ffg901 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=544 inst/S00_AXIS_ACLK=544 inst/S01_AXIS_ACLK=544 | *ACLK | 544 | 431 | 626 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||||
xc7k480t | ffg901 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=440 inst/M01_AXIS_ACLK=440 inst/S00_AXIS_ACLK=440 inst/S01_AXIS_ACLK=440 | *ACLK | 440 | 525 | 641 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||||||
xc7k480t | ffg901 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=440 inst/S00_AXIS_ACLK=440 inst/S01_AXIS_ACLK=440 inst/S02_AXIS_ACLK=440 inst/S03_AXIS_ACLK=440 | *ACLK | 440 | 313 | 392 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||
xc7k480t | ffg901 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=450 inst/S00_AXIS_ACLK=450 inst/S01_AXIS_ACLK=450 inst/S02_AXIS_ACLK=450 inst/S03_AXIS_ACLK=450 | *ACLK | 450 | 996 | 1254 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||
xc7k480t | ffg901 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=435 inst/S00_AXIS_ACLK=435 inst/S01_AXIS_ACLK=435 inst/S02_AXIS_ACLK=435 inst/S03_AXIS_ACLK=435 | *ACLK | 435 | 3017 | 4716 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | ||||||||
xc7k480t | ffg901 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=413 inst/M01_AXIS_ACLK=413 inst/M02_AXIS_ACLK=413 inst/M03_AXIS_ACLK=413 inst/S00_AXIS_ACLK=413 inst/S01_AXIS_ACLK=413 inst/S02_AXIS_ACLK=413 inst/S03_AXIS_ACLK=413 | *ACLK | 413 | 589 | 497 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||
xc7k480t | ffg901 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=402 inst/M01_AXIS_ACLK=402 inst/M02_AXIS_ACLK=402 inst/M03_AXIS_ACLK=402 inst/S00_AXIS_ACLK=402 inst/S01_AXIS_ACLK=402 inst/S02_AXIS_ACLK=402 inst/S03_AXIS_ACLK=402 | *ACLK | 402 | 1448 | 1361 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 | |||||
xc7k480t | ffg901 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=347 inst/M01_AXIS_ACLK=347 inst/M02_AXIS_ACLK=347 inst/M03_AXIS_ACLK=347 inst/S00_AXIS_ACLK=347 inst/S01_AXIS_ACLK=347 inst/S02_AXIS_ACLK=347 inst/S03_AXIS_ACLK=347 | *ACLK | 347 | 7202 | 4817 | 0 | 0 | 0 | PRODUCTION 1.12 2017-02-17 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xcku115 | flva1517 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=680 | *ACLK | 680 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcku115 | flva1517 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=680 | *ACLK | 680 | 156 | 303 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcku115 | flva1517 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=735 | *ACLK | 735 | 137 | 391 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcku115 | flva1517 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=461 inst/M01_AXIS_ACLK=461 inst/M02_AXIS_ACLK=461 inst/M03_AXIS_ACLK=461 | *ACLK | 461 | 1163 | 4486 | 0 | 8 | 1 | PRODUCTION 1.26 12-04-2018 | ||||
xcku115 | flva1517 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=741 inst/S00_AXIS_ACLK=741 | *ACLK | 741 | 122 | 333 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||
xcku115 | flva1517 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=489 inst/S00_AXIS_ACLK=489 | *ACLK | 489 | 51 | 210 | 0 | 2 | 1 | PRODUCTION 1.26 12-04-2018 | |||||||||||
xcku115 | flva1517 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=505 inst/S00_AXIS_ACLK=505 | *ACLK | 505 | 67 | 220 | 0 | 2 | 1 | PRODUCTION 1.26 12-04-2018 | |||||||||||
xcku115 | flva1517 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=905 inst/S00_AXIS_ACLK=905 | *ACLK | 905 | 24 | 195 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcku115 | flva1517 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=855 inst/S00_AXIS_ACLK=855 | *ACLK | 855 | 90 | 193 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcku115 | flva1517 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=822 inst/S00_AXIS_ACLK=822 | *ACLK | 822 | 23 | 735 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcku115 | flva1517 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=866 inst/S00_AXIS_ACLK=866 | *ACLK | 866 | 313 | 733 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcku115 | flva1517 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=965 inst/S00_AXIS_ACLK=965 | *ACLK | 965 | 46 | 83 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcku115 | flva1517 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=833 inst/S00_AXIS_ACLK=833 | *ACLK | 833 | 154 | 299 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcku115 | flva1517 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=774 inst/S00_AXIS_ACLK=774 | *ACLK | 774 | 586 | 1164 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcku115 | flva1517 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=708 inst/M01_AXIS_ACLK=708 inst/S00_AXIS_ACLK=708 | *ACLK | 708 | 169 | 311 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||
xcku115 | flva1517 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=757 inst/M01_AXIS_ACLK=757 inst/M02_AXIS_ACLK=757 inst/M03_AXIS_ACLK=757 inst/S00_AXIS_ACLK=757 | *ACLK | 757 | 72 | 100 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcku115 | flva1517 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=658 inst/M01_AXIS_ACLK=658 inst/M02_AXIS_ACLK=658 inst/M03_AXIS_ACLK=658 inst/S00_AXIS_ACLK=658 | *ACLK | 658 | 172 | 316 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcku115 | flva1517 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=582 inst/M01_AXIS_ACLK=582 inst/M02_AXIS_ACLK=582 inst/M03_AXIS_ACLK=582 inst/S00_AXIS_ACLK=582 | *ACLK | 582 | 608 | 1181 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcku115 | flva1517 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=697 inst/S00_AXIS_ACLK=697 inst/S01_AXIS_ACLK=697 | *ACLK | 697 | 428 | 628 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||
xcku115 | flva1517 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=571 inst/M01_AXIS_ACLK=571 inst/S00_AXIS_ACLK=571 inst/S01_AXIS_ACLK=571 | *ACLK | 571 | 525 | 641 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||
xcku115 | flva1517 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=588 inst/S00_AXIS_ACLK=588 inst/S01_AXIS_ACLK=588 inst/S02_AXIS_ACLK=588 inst/S03_AXIS_ACLK=588 | *ACLK | 588 | 318 | 390 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcku115 | flva1517 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=555 inst/S00_AXIS_ACLK=555 inst/S01_AXIS_ACLK=555 inst/S02_AXIS_ACLK=555 inst/S03_AXIS_ACLK=555 | *ACLK | 555 | 998 | 1254 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcku115 | flva1517 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=544 inst/S00_AXIS_ACLK=544 inst/S01_AXIS_ACLK=544 inst/S02_AXIS_ACLK=544 inst/S03_AXIS_ACLK=544 | *ACLK | 544 | 3015 | 4716 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcku115 | flva1517 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=527 inst/M01_AXIS_ACLK=527 inst/M02_AXIS_ACLK=527 inst/M03_AXIS_ACLK=527 inst/S00_AXIS_ACLK=527 inst/S01_AXIS_ACLK=527 inst/S02_AXIS_ACLK=527 inst/S03_AXIS_ACLK=527 | *ACLK | 527 | 567 | 498 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||
xcku115 | flva1517 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=505 inst/M01_AXIS_ACLK=505 inst/M02_AXIS_ACLK=505 inst/M03_AXIS_ACLK=505 inst/S00_AXIS_ACLK=505 inst/S01_AXIS_ACLK=505 inst/S02_AXIS_ACLK=505 inst/S03_AXIS_ACLK=505 | *ACLK | 505 | 1133 | 1362 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||
xcku115 | flva1517 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=435 inst/M01_AXIS_ACLK=435 inst/M02_AXIS_ACLK=435 inst/M03_AXIS_ACLK=435 inst/S00_AXIS_ACLK=435 inst/S01_AXIS_ACLK=435 inst/S02_AXIS_ACLK=435 inst/S03_AXIS_ACLK=435 | *ACLK | 435 | 6044 | 4821 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xcku15p | ffva1156 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=932 | *ACLK | 932 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||||
xcku15p | ffva1156 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=927 | *ACLK | 927 | 156 | 302 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||||
xcku15p | ffva1156 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=817 | *ACLK | 817 | 136 | 391 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||||
xcku15p | ffva1156 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=647 inst/M01_AXIS_ACLK=647 inst/M02_AXIS_ACLK=647 inst/M03_AXIS_ACLK=647 | *ACLK | 647 | 1588 | 4484 | 0 | 8 | 1 | PRODUCTION 1.29 05-01-2022 | ||||
xcku15p | ffva1156 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=938 inst/S00_AXIS_ACLK=938 | *ACLK | 938 | 125 | 332 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||||||||
xcku15p | ffva1156 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=680 inst/S00_AXIS_ACLK=680 | *ACLK | 680 | 53 | 210 | 0 | 2 | 1 | PRODUCTION 1.29 05-01-2022 | |||||||||||
xcku15p | ffva1156 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=675 inst/S00_AXIS_ACLK=675 | *ACLK | 675 | 72 | 220 | 0 | 2 | 1 | PRODUCTION 1.29 05-01-2022 | |||||||||||
xcku15p | ffva1156 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=1289 inst/S00_AXIS_ACLK=1289 | *ACLK | 1288 | 25 | 195 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||||||||||
xcku15p | ffva1156 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=1211 inst/S00_AXIS_ACLK=1211 | *ACLK | 1211 | 91 | 193 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||||||||||
xcku15p | ffva1156 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=1058 inst/S00_AXIS_ACLK=1058 | *ACLK | 1058 | 23 | 736 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||||||||||
xcku15p | ffva1156 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=1149 inst/S00_AXIS_ACLK=1149 | *ACLK | 1150 | 313 | 733 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||||||||||
xcku15p | ffva1156 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=1311 inst/S00_AXIS_ACLK=1311 | *ACLK | 1310 | 44 | 83 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||||
xcku15p | ffva1156 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=1140 inst/S00_AXIS_ACLK=1140 | *ACLK | 1140 | 144 | 299 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||||
xcku15p | ffva1156 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=1047 inst/S00_AXIS_ACLK=1047 | *ACLK | 1047 | 588 | 1164 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||||
xcku15p | ffva1156 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=960 inst/M01_AXIS_ACLK=960 inst/S00_AXIS_ACLK=960 | *ACLK | 960 | 168 | 310 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||
xcku15p | ffva1156 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=1003 inst/M01_AXIS_ACLK=1003 inst/M02_AXIS_ACLK=1003 inst/M03_AXIS_ACLK=1003 inst/S00_AXIS_ACLK=1003 | *ACLK | 1003 | 69 | 101 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||
xcku15p | ffva1156 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=905 inst/M01_AXIS_ACLK=905 inst/M02_AXIS_ACLK=905 inst/M03_AXIS_ACLK=905 inst/S00_AXIS_ACLK=905 | *ACLK | 905 | 171 | 316 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||
xcku15p | ffva1156 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=785 inst/M01_AXIS_ACLK=785 inst/M02_AXIS_ACLK=785 inst/M03_AXIS_ACLK=785 inst/S00_AXIS_ACLK=785 | *ACLK | 785 | 610 | 1181 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||
xcku15p | ffva1156 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=943 inst/S00_AXIS_ACLK=943 inst/S01_AXIS_ACLK=943 | *ACLK | 943 | 417 | 626 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||||
xcku15p | ffva1156 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=785 inst/M01_AXIS_ACLK=785 inst/S00_AXIS_ACLK=785 inst/S01_AXIS_ACLK=785 | *ACLK | 785 | 499 | 641 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||||||
xcku15p | ffva1156 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=872 inst/S00_AXIS_ACLK=872 inst/S01_AXIS_ACLK=872 inst/S02_AXIS_ACLK=872 inst/S03_AXIS_ACLK=872 | *ACLK | 872 | 320 | 390 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||
xcku15p | ffva1156 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=811 inst/S00_AXIS_ACLK=811 inst/S01_AXIS_ACLK=811 inst/S02_AXIS_ACLK=811 inst/S03_AXIS_ACLK=811 | *ACLK | 811 | 990 | 1254 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||
xcku15p | ffva1156 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=680 inst/S00_AXIS_ACLK=680 inst/S01_AXIS_ACLK=680 inst/S02_AXIS_ACLK=680 inst/S03_AXIS_ACLK=680 | *ACLK | 680 | 3009 | 4716 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | ||||||||
xcku15p | ffva1156 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=779 inst/M01_AXIS_ACLK=779 inst/M02_AXIS_ACLK=779 inst/M03_AXIS_ACLK=779 inst/S00_AXIS_ACLK=779 inst/S01_AXIS_ACLK=779 inst/S02_AXIS_ACLK=779 inst/S03_AXIS_ACLK=779 | *ACLK | 779 | 577 | 497 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||
xcku15p | ffva1156 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=713 inst/M01_AXIS_ACLK=713 inst/M02_AXIS_ACLK=713 inst/M03_AXIS_ACLK=713 inst/S00_AXIS_ACLK=713 inst/S01_AXIS_ACLK=713 inst/S02_AXIS_ACLK=713 inst/S03_AXIS_ACLK=713 | *ACLK | 713 | 1429 | 1361 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 | |||||
xcku15p | ffva1156 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=653 inst/M01_AXIS_ACLK=653 inst/M02_AXIS_ACLK=653 inst/M03_AXIS_ACLK=653 inst/S00_AXIS_ACLK=653 inst/S01_AXIS_ACLK=653 inst/S02_AXIS_ACLK=653 inst/S03_AXIS_ACLK=653 | *ACLK | 653 | 7208 | 4821 | 0 | 0 | 0 | PRODUCTION 1.29 05-01-2022 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xc7s100 | fgga484 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=489 | *ACLK | 489 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7s100 | fgga484 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=440 | *ACLK | 440 | 155 | 301 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7s100 | fgga484 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=385 | *ACLK | 385 | 153 | 391 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7s100 | fgga484 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=292 inst/M01_AXIS_ACLK=292 inst/M02_AXIS_ACLK=292 inst/M03_AXIS_ACLK=292 | *ACLK | 292 | 1316 | 4484 | 0 | 8 | 1 | PRODUCTION 1.23 2018-06-13 | ||||
xc7s100 | fgga484 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=407 inst/S00_AXIS_ACLK=407 | *ACLK | 407 | 136 | 332 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||
xc7s100 | fgga484 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=330 inst/S00_AXIS_ACLK=330 | *ACLK | 330 | 54 | 210 | 0 | 2 | 1 | PRODUCTION 1.23 2018-06-13 | |||||||||||
xc7s100 | fgga484 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=330 inst/S00_AXIS_ACLK=330 | *ACLK | 330 | 66 | 220 | 0 | 2 | 1 | PRODUCTION 1.23 2018-06-13 | |||||||||||
xc7s100 | fgga484 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=511 inst/S00_AXIS_ACLK=511 | *ACLK | 511 | 23 | 195 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7s100 | fgga484 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=440 inst/S00_AXIS_ACLK=440 | *ACLK | 440 | 94 | 193 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7s100 | fgga484 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=435 inst/S00_AXIS_ACLK=435 | *ACLK | 435 | 21 | 735 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7s100 | fgga484 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=450 inst/S00_AXIS_ACLK=450 | *ACLK | 450 | 316 | 733 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||||||
xc7s100 | fgga484 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=560 inst/S00_AXIS_ACLK=560 | *ACLK | 560 | 48 | 83 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7s100 | fgga484 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=500 inst/S00_AXIS_ACLK=500 | *ACLK | 500 | 155 | 299 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7s100 | fgga484 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=429 inst/S00_AXIS_ACLK=429 | *ACLK | 429 | 588 | 1164 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||||
xc7s100 | fgga484 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=385 inst/M01_AXIS_ACLK=385 inst/S00_AXIS_ACLK=385 | *ACLK | 385 | 168 | 310 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||
xc7s100 | fgga484 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=396 inst/M01_AXIS_ACLK=396 inst/M02_AXIS_ACLK=396 inst/M03_AXIS_ACLK=396 inst/S00_AXIS_ACLK=396 | *ACLK | 396 | 73 | 101 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7s100 | fgga484 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=352 inst/M01_AXIS_ACLK=352 inst/M02_AXIS_ACLK=352 inst/M03_AXIS_ACLK=352 inst/S00_AXIS_ACLK=352 | *ACLK | 352 | 181 | 316 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7s100 | fgga484 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=319 inst/M01_AXIS_ACLK=319 inst/M02_AXIS_ACLK=319 inst/M03_AXIS_ACLK=319 inst/S00_AXIS_ACLK=319 | *ACLK | 319 | 327 | 1181 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7s100 | fgga484 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=396 inst/S00_AXIS_ACLK=396 inst/S01_AXIS_ACLK=396 | *ACLK | 396 | 428 | 626 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||||
xc7s100 | fgga484 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=325 inst/M01_AXIS_ACLK=325 inst/S00_AXIS_ACLK=325 inst/S01_AXIS_ACLK=325 | *ACLK | 325 | 381 | 641 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||||||
xc7s100 | fgga484 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=292 inst/S00_AXIS_ACLK=292 inst/S01_AXIS_ACLK=292 inst/S02_AXIS_ACLK=292 inst/S03_AXIS_ACLK=292 | *ACLK | 292 | 314 | 390 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7s100 | fgga484 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=303 inst/S00_AXIS_ACLK=303 inst/S01_AXIS_ACLK=303 inst/S02_AXIS_ACLK=303 inst/S03_AXIS_ACLK=303 | *ACLK | 303 | 985 | 1254 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7s100 | fgga484 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=281 inst/S00_AXIS_ACLK=281 inst/S01_AXIS_ACLK=281 inst/S02_AXIS_ACLK=281 inst/S03_AXIS_ACLK=281 | *ACLK | 281 | 3013 | 4716 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | ||||||||
xc7s100 | fgga484 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=286 inst/M01_AXIS_ACLK=286 inst/M02_AXIS_ACLK=286 inst/M03_AXIS_ACLK=286 inst/S00_AXIS_ACLK=286 inst/S01_AXIS_ACLK=286 inst/S02_AXIS_ACLK=286 inst/S03_AXIS_ACLK=286 | *ACLK | 286 | 503 | 497 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||
xc7s100 | fgga484 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=265 inst/M01_AXIS_ACLK=265 inst/M02_AXIS_ACLK=265 inst/M03_AXIS_ACLK=265 inst/S00_AXIS_ACLK=265 inst/S01_AXIS_ACLK=265 inst/S02_AXIS_ACLK=265 inst/S03_AXIS_ACLK=265 | *ACLK | 265 | 1137 | 1361 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 | |||||
xc7s100 | fgga484 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=232 inst/M01_AXIS_ACLK=232 inst/M02_AXIS_ACLK=232 inst/M03_AXIS_ACLK=232 inst/S00_AXIS_ACLK=232 inst/S01_AXIS_ACLK=232 inst/S02_AXIS_ACLK=232 inst/S03_AXIS_ACLK=232 | *ACLK | 232 | 6043 | 4817 | 0 | 0 | 0 | PRODUCTION 1.23 2018-06-13 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xc7vx1140t | flg1926 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=527 | *ACLK | 527 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||||
xc7vx1140t | flg1926 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=511 | *ACLK | 511 | 156 | 301 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||||
xc7vx1140t | flg1926 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=610 | *ACLK | 610 | 152 | 391 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||||
xc7vx1140t | flg1926 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=380 inst/M01_AXIS_ACLK=380 inst/M02_AXIS_ACLK=380 inst/M03_AXIS_ACLK=380 | *ACLK | 380 | 1606 | 4484 | 0 | 8 | 1 | PRODUCTION 1.11 2014-09-11 | ||||
xc7vx1140t | flg1926 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=647 inst/S00_AXIS_ACLK=647 | *ACLK | 647 | 140 | 336 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||||||||
xc7vx1140t | flg1926 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=472 inst/S00_AXIS_ACLK=472 | *ACLK | 472 | 56 | 65 | 0 | 2 | 1 | PRODUCTION 1.11 2014-09-11 | |||||||||||
xc7vx1140t | flg1926 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=472 inst/S00_AXIS_ACLK=472 | *ACLK | 472 | 72 | 75 | 0 | 2 | 1 | PRODUCTION 1.11 2014-09-11 | |||||||||||
xc7vx1140t | flg1926 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=708 inst/S00_AXIS_ACLK=708 | *ACLK | 708 | 23 | 195 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||||||||||
xc7vx1140t | flg1926 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=713 inst/S00_AXIS_ACLK=713 | *ACLK | 713 | 95 | 194 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||||||||||
xc7vx1140t | flg1926 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=653 inst/S00_AXIS_ACLK=653 | *ACLK | 653 | 23 | 735 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||||||||||
xc7vx1140t | flg1926 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=615 inst/S00_AXIS_ACLK=615 | *ACLK | 615 | 317 | 733 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||||||||||
xc7vx1140t | flg1926 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=822 inst/S00_AXIS_ACLK=822 | *ACLK | 822 | 49 | 84 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||||
xc7vx1140t | flg1926 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=697 inst/S00_AXIS_ACLK=697 | *ACLK | 697 | 158 | 299 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||||
xc7vx1140t | flg1926 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=582 inst/S00_AXIS_ACLK=582 | *ACLK | 582 | 589 | 1168 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||||
xc7vx1140t | flg1926 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=588 inst/M01_AXIS_ACLK=588 inst/S00_AXIS_ACLK=588 | *ACLK | 588 | 174 | 311 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||
xc7vx1140t | flg1926 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=577 inst/M01_AXIS_ACLK=577 inst/M02_AXIS_ACLK=577 inst/M03_AXIS_ACLK=577 inst/S00_AXIS_ACLK=577 | *ACLK | 577 | 74 | 102 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||
xc7vx1140t | flg1926 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=549 inst/M01_AXIS_ACLK=549 inst/M02_AXIS_ACLK=549 inst/M03_AXIS_ACLK=549 inst/S00_AXIS_ACLK=549 | *ACLK | 549 | 184 | 316 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||
xc7vx1140t | flg1926 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=435 inst/M01_AXIS_ACLK=435 inst/M02_AXIS_ACLK=435 inst/M03_AXIS_ACLK=435 inst/S00_AXIS_ACLK=435 | *ACLK | 435 | 616 | 1181 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||
xc7vx1140t | flg1926 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=571 inst/S00_AXIS_ACLK=571 inst/S01_AXIS_ACLK=571 | *ACLK | 571 | 432 | 626 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||||
xc7vx1140t | flg1926 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=472 inst/M01_AXIS_ACLK=472 inst/S00_AXIS_ACLK=472 inst/S01_AXIS_ACLK=472 | *ACLK | 472 | 527 | 641 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||||||
xc7vx1140t | flg1926 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=450 inst/S00_AXIS_ACLK=450 inst/S01_AXIS_ACLK=450 inst/S02_AXIS_ACLK=450 inst/S03_AXIS_ACLK=450 | *ACLK | 450 | 317 | 391 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||
xc7vx1140t | flg1926 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=440 inst/S00_AXIS_ACLK=440 inst/S01_AXIS_ACLK=440 inst/S02_AXIS_ACLK=440 inst/S03_AXIS_ACLK=440 | *ACLK | 440 | 995 | 1254 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||
xc7vx1140t | flg1926 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=402 inst/S00_AXIS_ACLK=402 inst/S01_AXIS_ACLK=402 inst/S02_AXIS_ACLK=402 inst/S03_AXIS_ACLK=402 | *ACLK | 402 | 3021 | 4716 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | ||||||||
xc7vx1140t | flg1926 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=418 inst/M01_AXIS_ACLK=418 inst/M02_AXIS_ACLK=418 inst/M03_AXIS_ACLK=418 inst/S00_AXIS_ACLK=418 inst/S01_AXIS_ACLK=418 inst/S02_AXIS_ACLK=418 inst/S03_AXIS_ACLK=418 | *ACLK | 418 | 587 | 497 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||
xc7vx1140t | flg1926 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=402 inst/M01_AXIS_ACLK=402 inst/M02_AXIS_ACLK=402 inst/M03_AXIS_ACLK=402 inst/S00_AXIS_ACLK=402 inst/S01_AXIS_ACLK=402 inst/S02_AXIS_ACLK=402 inst/S03_AXIS_ACLK=402 | *ACLK | 402 | 1452 | 1361 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 | |||||
xc7vx1140t | flg1926 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=341 inst/M01_AXIS_ACLK=341 inst/M02_AXIS_ACLK=341 inst/M03_AXIS_ACLK=341 inst/S00_AXIS_ACLK=341 inst/S01_AXIS_ACLK=341 inst/S02_AXIS_ACLK=341 inst/S03_AXIS_ACLK=341 | *ACLK | 341 | 7221 | 4817 | 0 | 0 | 0 | PRODUCTION 1.11 2014-09-11 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xcvu440 | flga2892 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=593 | *ACLK | 593 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcvu440 | flga2892 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=566 | *ACLK | 566 | 155 | 301 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcvu440 | flga2892 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=675 | *ACLK | 675 | 135 | 391 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcvu440 | flga2892 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=440 inst/M01_AXIS_ACLK=440 inst/M02_AXIS_ACLK=440 inst/M03_AXIS_ACLK=440 | *ACLK | 440 | 1162 | 4485 | 0 | 8 | 1 | PRODUCTION 1.26 12-04-2018 | ||||
xcvu440 | flga2892 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=746 inst/S00_AXIS_ACLK=746 | *ACLK | 746 | 122 | 332 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||
xcvu440 | flga2892 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=489 inst/S00_AXIS_ACLK=489 | *ACLK | 489 | 51 | 211 | 0 | 2 | 1 | PRODUCTION 1.26 12-04-2018 | |||||||||||
xcvu440 | flga2892 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=505 inst/S00_AXIS_ACLK=505 | *ACLK | 505 | 69 | 221 | 0 | 2 | 1 | PRODUCTION 1.26 12-04-2018 | |||||||||||
xcvu440 | flga2892 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=954 inst/S00_AXIS_ACLK=954 | *ACLK | 954 | 24 | 195 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcvu440 | flga2892 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=833 inst/S00_AXIS_ACLK=833 | *ACLK | 833 | 90 | 194 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcvu440 | flga2892 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=790 inst/S00_AXIS_ACLK=790 | *ACLK | 790 | 23 | 735 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcvu440 | flga2892 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=866 inst/S00_AXIS_ACLK=866 | *ACLK | 866 | 313 | 733 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||||||
xcvu440 | flga2892 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=965 inst/S00_AXIS_ACLK=965 | *ACLK | 965 | 45 | 83 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcvu440 | flga2892 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=839 inst/S00_AXIS_ACLK=839 | *ACLK | 839 | 155 | 299 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcvu440 | flga2892 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=800 inst/S00_AXIS_ACLK=800 | *ACLK | 800 | 589 | 1164 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||||
xcvu440 | flga2892 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=757 inst/M01_AXIS_ACLK=757 inst/S00_AXIS_ACLK=757 | *ACLK | 757 | 171 | 310 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||
xcvu440 | flga2892 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=713 inst/M01_AXIS_ACLK=713 inst/M02_AXIS_ACLK=713 inst/M03_AXIS_ACLK=713 inst/S00_AXIS_ACLK=713 | *ACLK | 713 | 64 | 101 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcvu440 | flga2892 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=631 inst/M01_AXIS_ACLK=631 inst/M02_AXIS_ACLK=631 inst/M03_AXIS_ACLK=631 inst/S00_AXIS_ACLK=631 | *ACLK | 631 | 176 | 316 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcvu440 | flga2892 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=544 inst/M01_AXIS_ACLK=544 inst/M02_AXIS_ACLK=544 inst/M03_AXIS_ACLK=544 inst/S00_AXIS_ACLK=544 | *ACLK | 544 | 612 | 1181 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcvu440 | flga2892 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=691 inst/S00_AXIS_ACLK=691 inst/S01_AXIS_ACLK=691 | *ACLK | 691 | 428 | 626 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||||
xcvu440 | flga2892 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=566 inst/M01_AXIS_ACLK=566 inst/S00_AXIS_ACLK=566 inst/S01_AXIS_ACLK=566 | *ACLK | 566 | 521 | 641 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||||||
xcvu440 | flga2892 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=599 inst/S00_AXIS_ACLK=599 inst/S01_AXIS_ACLK=599 inst/S02_AXIS_ACLK=599 inst/S03_AXIS_ACLK=599 | *ACLK | 599 | 326 | 392 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcvu440 | flga2892 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=555 inst/S00_AXIS_ACLK=555 inst/S01_AXIS_ACLK=555 inst/S02_AXIS_ACLK=555 inst/S03_AXIS_ACLK=555 | *ACLK | 555 | 993 | 1254 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcvu440 | flga2892 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=571 inst/S00_AXIS_ACLK=571 inst/S01_AXIS_ACLK=571 inst/S02_AXIS_ACLK=571 inst/S03_AXIS_ACLK=571 | *ACLK | 571 | 3016 | 4716 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | ||||||||
xcvu440 | flga2892 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=511 inst/M01_AXIS_ACLK=511 inst/M02_AXIS_ACLK=511 inst/M03_AXIS_ACLK=511 inst/S00_AXIS_ACLK=511 inst/S01_AXIS_ACLK=511 inst/S02_AXIS_ACLK=511 inst/S03_AXIS_ACLK=511 | *ACLK | 511 | 500 | 498 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||
xcvu440 | flga2892 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=527 inst/M01_AXIS_ACLK=527 inst/M02_AXIS_ACLK=527 inst/M03_AXIS_ACLK=527 inst/S00_AXIS_ACLK=527 inst/S01_AXIS_ACLK=527 inst/S02_AXIS_ACLK=527 inst/S03_AXIS_ACLK=527 | *ACLK | 527 | 1433 | 1365 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 | |||||
xcvu440 | flga2892 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=456 inst/M01_AXIS_ACLK=456 inst/M02_AXIS_ACLK=456 inst/M03_AXIS_ACLK=456 inst/S00_AXIS_ACLK=456 inst/S01_AXIS_ACLK=456 inst/S02_AXIS_ACLK=456 inst/S03_AXIS_ACLK=456 | *ACLK | 456 | 6047 | 4821 | 0 | 0 | 0 | PRODUCTION 1.26 12-04-2018 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xcvu13p | fhga2104 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=636 | *ACLK | 636 | 153 | 300 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||||
xcvu13p | fhga2104 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=669 | *ACLK | 669 | 155 | 301 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||||
xcvu13p | fhga2104 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=833 | *ACLK | 833 | 138 | 391 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||||
xcvu13p | fhga2104 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=440 inst/M01_AXIS_ACLK=440 inst/M02_AXIS_ACLK=440 inst/M03_AXIS_ACLK=440 | *ACLK | 440 | 1152 | 4484 | 0 | 8 | 1 | PRODUCTION 1.28 03-30-2022 | ||||
xcvu13p | fhga2104 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=938 inst/S00_AXIS_ACLK=938 | *ACLK | 938 | 124 | 332 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||||||||
xcvu13p | fhga2104 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=658 inst/S00_AXIS_ACLK=658 | *ACLK | 658 | 55 | 210 | 0 | 2 | 1 | PRODUCTION 1.28 03-30-2022 | |||||||||||
xcvu13p | fhga2104 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=680 inst/S00_AXIS_ACLK=680 | *ACLK | 680 | 71 | 220 | 0 | 2 | 1 | PRODUCTION 1.28 03-30-2022 | |||||||||||
xcvu13p | fhga2104 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=1348 inst/S00_AXIS_ACLK=1348 | *ACLK | 1347 | 25 | 195 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||||||||||
xcvu13p | fhga2104 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=1227 inst/S00_AXIS_ACLK=1227 | *ACLK | 1227 | 90 | 194 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||||||||||
xcvu13p | fhga2104 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=1149 inst/S00_AXIS_ACLK=1149 | *ACLK | 1150 | 24 | 735 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||||||||||
xcvu13p | fhga2104 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=1063 inst/S00_AXIS_ACLK=1063 | *ACLK | 1063 | 313 | 733 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||||||||||
xcvu13p | fhga2104 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=1233 inst/S00_AXIS_ACLK=1233 | *ACLK | 1233 | 47 | 83 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||||
xcvu13p | fhga2104 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=1167 inst/S00_AXIS_ACLK=1167 | *ACLK | 1167 | 157 | 299 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||||
xcvu13p | fhga2104 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=981 inst/S00_AXIS_ACLK=981 | *ACLK | 981 | 588 | 1164 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||||
xcvu13p | fhga2104 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=981 inst/M01_AXIS_ACLK=981 inst/S00_AXIS_ACLK=981 | *ACLK | 981 | 158 | 311 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||
xcvu13p | fhga2104 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=1025 inst/M01_AXIS_ACLK=1025 inst/M02_AXIS_ACLK=1025 inst/M03_AXIS_ACLK=1025 inst/S00_AXIS_ACLK=1025 | *ACLK | 1025 | 64 | 100 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||
xcvu13p | fhga2104 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=883 inst/M01_AXIS_ACLK=883 inst/M02_AXIS_ACLK=883 inst/M03_AXIS_ACLK=883 inst/S00_AXIS_ACLK=883 | *ACLK | 883 | 165 | 316 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||
xcvu13p | fhga2104 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=768 inst/M01_AXIS_ACLK=768 inst/M02_AXIS_ACLK=768 inst/M03_AXIS_ACLK=768 inst/S00_AXIS_ACLK=768 | *ACLK | 768 | 608 | 1181 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||
xcvu13p | fhga2104 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=943 inst/S00_AXIS_ACLK=943 inst/S01_AXIS_ACLK=943 | *ACLK | 943 | 409 | 626 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||||
xcvu13p | fhga2104 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=822 inst/M01_AXIS_ACLK=822 inst/S00_AXIS_ACLK=822 inst/S01_AXIS_ACLK=822 | *ACLK | 822 | 522 | 641 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||||||
xcvu13p | fhga2104 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=817 inst/S00_AXIS_ACLK=817 inst/S01_AXIS_ACLK=817 inst/S02_AXIS_ACLK=817 inst/S03_AXIS_ACLK=817 | *ACLK | 817 | 319 | 390 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||
xcvu13p | fhga2104 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=822 inst/S00_AXIS_ACLK=822 inst/S01_AXIS_ACLK=822 inst/S02_AXIS_ACLK=822 inst/S03_AXIS_ACLK=822 | *ACLK | 822 | 989 | 1254 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||
xcvu13p | fhga2104 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=615 inst/S00_AXIS_ACLK=615 inst/S01_AXIS_ACLK=615 inst/S02_AXIS_ACLK=615 inst/S03_AXIS_ACLK=615 | *ACLK | 615 | 3010 | 4716 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | ||||||||
xcvu13p | fhga2104 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=702 inst/M01_AXIS_ACLK=702 inst/M02_AXIS_ACLK=702 inst/M03_AXIS_ACLK=702 inst/S00_AXIS_ACLK=702 inst/S01_AXIS_ACLK=702 inst/S02_AXIS_ACLK=702 inst/S03_AXIS_ACLK=702 | *ACLK | 702 | 577 | 497 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||
xcvu13p | fhga2104 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=730 inst/M01_AXIS_ACLK=730 inst/M02_AXIS_ACLK=730 inst/M03_AXIS_ACLK=730 inst/S00_AXIS_ACLK=730 inst/S01_AXIS_ACLK=730 inst/S02_AXIS_ACLK=730 inst/S03_AXIS_ACLK=730 | *ACLK | 730 | 1430 | 1361 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 | |||||
xcvu13p | fhga2104 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=691 inst/M01_AXIS_ACLK=691 inst/M02_AXIS_ACLK=691 inst/M03_AXIS_ACLK=691 inst/S00_AXIS_ACLK=691 inst/S01_AXIS_ACLK=691 inst/S02_AXIS_ACLK=691 inst/S03_AXIS_ACLK=691 | *ACLK | 691 | 7215 | 4821 | 0 | 0 | 0 | PRODUCTION 1.28 03-30-2022 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xc7z100 | ffg900 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=708 | *ACLK | 708 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||||
xc7z100 | ffg900 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=631 | *ACLK | 631 | 156 | 301 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||||
xc7z100 | ffg900 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=636 | *ACLK | 636 | 153 | 391 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||||
xc7z100 | ffg900 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=396 inst/M01_AXIS_ACLK=396 inst/M02_AXIS_ACLK=396 inst/M03_AXIS_ACLK=396 | *ACLK | 396 | 1610 | 4484 | 0 | 8 | 1 | PRODUCTION 1.12 2019-11-22 | ||||
xc7z100 | ffg900 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=636 inst/S00_AXIS_ACLK=636 | *ACLK | 636 | 139 | 332 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||||||||
xc7z100 | ffg900 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=402 inst/S00_AXIS_ACLK=402 | *ACLK | 402 | 56 | 210 | 0 | 2 | 1 | PRODUCTION 1.12 2019-11-22 | |||||||||||
xc7z100 | ffg900 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=413 inst/S00_AXIS_ACLK=413 | *ACLK | 413 | 72 | 220 | 0 | 2 | 1 | PRODUCTION 1.12 2019-11-22 | |||||||||||
xc7z100 | ffg900 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=697 inst/S00_AXIS_ACLK=697 | *ACLK | 697 | 23 | 195 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||||||||||
xc7z100 | ffg900 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=724 inst/S00_AXIS_ACLK=724 | *ACLK | 724 | 95 | 195 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||||||||||
xc7z100 | ffg900 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=604 inst/S00_AXIS_ACLK=604 | *ACLK | 604 | 25 | 735 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||||||||||
xc7z100 | ffg900 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=636 inst/S00_AXIS_ACLK=636 | *ACLK | 636 | 317 | 733 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||||||||||
xc7z100 | ffg900 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=735 inst/S00_AXIS_ACLK=735 | *ACLK | 735 | 48 | 83 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||||
xc7z100 | ffg900 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=713 inst/S00_AXIS_ACLK=713 | *ACLK | 713 | 157 | 299 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||||
xc7z100 | ffg900 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=582 inst/S00_AXIS_ACLK=582 | *ACLK | 582 | 589 | 1164 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||||
xc7z100 | ffg900 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=604 inst/M01_AXIS_ACLK=604 inst/S00_AXIS_ACLK=604 | *ACLK | 604 | 172 | 310 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||
xc7z100 | ffg900 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=582 inst/M01_AXIS_ACLK=582 inst/M02_AXIS_ACLK=582 inst/M03_AXIS_ACLK=582 inst/S00_AXIS_ACLK=582 | *ACLK | 582 | 76 | 100 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||
xc7z100 | ffg900 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=500 inst/M01_AXIS_ACLK=500 inst/M02_AXIS_ACLK=500 inst/M03_AXIS_ACLK=500 inst/S00_AXIS_ACLK=500 | *ACLK | 500 | 182 | 316 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||
xc7z100 | ffg900 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=440 inst/M01_AXIS_ACLK=440 inst/M02_AXIS_ACLK=440 inst/M03_AXIS_ACLK=440 inst/S00_AXIS_ACLK=440 | *ACLK | 440 | 617 | 1181 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||
xc7z100 | ffg900 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=560 inst/S00_AXIS_ACLK=560 inst/S01_AXIS_ACLK=560 | *ACLK | 560 | 427 | 627 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||||
xc7z100 | ffg900 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=494 inst/M01_AXIS_ACLK=494 inst/S00_AXIS_ACLK=494 inst/S01_AXIS_ACLK=494 | *ACLK | 494 | 524 | 641 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||||||
xc7z100 | ffg900 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=472 inst/S00_AXIS_ACLK=472 inst/S01_AXIS_ACLK=472 inst/S02_AXIS_ACLK=472 inst/S03_AXIS_ACLK=472 | *ACLK | 472 | 315 | 392 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||
xc7z100 | ffg900 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=440 inst/S00_AXIS_ACLK=440 inst/S01_AXIS_ACLK=440 inst/S02_AXIS_ACLK=440 inst/S03_AXIS_ACLK=440 | *ACLK | 440 | 989 | 1254 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||
xc7z100 | ffg900 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=450 inst/S00_AXIS_ACLK=450 inst/S01_AXIS_ACLK=450 inst/S02_AXIS_ACLK=450 inst/S03_AXIS_ACLK=450 | *ACLK | 450 | 3019 | 4716 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | ||||||||
xc7z100 | ffg900 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=424 inst/M01_AXIS_ACLK=424 inst/M02_AXIS_ACLK=424 inst/M03_AXIS_ACLK=424 inst/S00_AXIS_ACLK=424 inst/S01_AXIS_ACLK=424 inst/S02_AXIS_ACLK=424 inst/S03_AXIS_ACLK=424 | *ACLK | 424 | 585 | 497 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||
xc7z100 | ffg900 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=380 inst/M01_AXIS_ACLK=380 inst/M02_AXIS_ACLK=380 inst/M03_AXIS_ACLK=380 inst/S00_AXIS_ACLK=380 inst/S01_AXIS_ACLK=380 inst/S02_AXIS_ACLK=380 inst/S03_AXIS_ACLK=380 | *ACLK | 380 | 1432 | 1361 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 | |||||
xc7z100 | ffg900 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=325 inst/M01_AXIS_ACLK=325 inst/M02_AXIS_ACLK=325 inst/M03_AXIS_ACLK=325 inst/S00_AXIS_ACLK=325 inst/S01_AXIS_ACLK=325 inst/S02_AXIS_ACLK=325 inst/S03_AXIS_ACLK=325 | *ACLK | 325 | 7200 | 4817 | 0 | 0 | 0 | PRODUCTION 1.12 2019-11-22 |
Part Information | Configuration Parameters | Performance and Resource Utilization | |||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Device | Package | Speed Grade | Configuration Name | C_NUM_SI_SLOTS |
C_NUM_MI_SLOTS |
SWITCH_TDATA_NUM_BYTES |
HAS_TSTRB |
HAS_TLAST |
HAS_TID |
M00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_REG_CONFIG |
S00_AXIS_TDATA_NUM_BYTES |
C_S00_AXIS_IS_ACLK_ASYNC |
C_S00_AXIS_ACLK_RATIO |
S00_AXIS_FIFO_MODE |
C_S00_AXIS_FIFO_DEPTH |
M01_AXIS_TDATA_NUM_BYTES |
S01_AXIS_TDATA_NUM_BYTES |
M02_AXIS_TDATA_NUM_BYTES |
S02_AXIS_TDATA_NUM_BYTES |
M03_AXIS_TDATA_NUM_BYTES |
S03_AXIS_TDATA_NUM_BYTES |
Fixed clocks (MHz) | Clock Input | Fmax (MHz) | LUTs | FFs | DSP48s | 36k BRAMs | 18k BRAMs | Speedfile Status |
xczu19eg | ffvb1517 | 2 | Clock converter: 1:4 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 48 | inst/M00_AXIS_ACLK=932 | *ACLK | 932 | 154 | 300 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||||
xczu19eg | ffvb1517 | 2 | Clock converter: 4:1 ratio, 128-bit | 16 | false | false | false | 16 | 16 | 3 | inst/M00_AXIS_ACLK=927 | *ACLK | 927 | 156 | 302 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||||
xczu19eg | ffvb1517 | 2 | Clock converter: asynchronous, 128-bit | 16 | false | false | false | 16 | 16 | 1 | inst/M00_AXIS_ACLK=817 | *ACLK | 817 | 136 | 391 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||||
xczu19eg | ffvb1517 | 2 | Complex interconnect: 1x4 Switch, 2:1 clock ratio, 128:256-bit upsizer, 512 depth FIFO and register slice input | 1 | 4 | 64 | false | false | false | 64 | 1 | 32 | 6 | 1_(Normal) | 512 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=647 inst/M01_AXIS_ACLK=647 inst/M02_AXIS_ACLK=647 inst/M03_AXIS_ACLK=647 | *ACLK | 647 | 1588 | 4484 | 0 | 8 | 1 | PRODUCTION 1.30 05-15-2022 | ||||
xczu19eg | ffvb1517 | 2 | Data FIFO: 16 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 16 | inst/M00_AXIS_ACLK=938 inst/S00_AXIS_ACLK=938 | *ACLK | 938 | 125 | 332 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||||||||
xczu19eg | ffvb1517 | 2 | Data FIFO: 128 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 128 | inst/M00_AXIS_ACLK=680 inst/S00_AXIS_ACLK=680 | *ACLK | 680 | 53 | 210 | 0 | 2 | 1 | PRODUCTION 1.30 05-15-2022 | |||||||||||
xczu19eg | ffvb1517 | 2 | Data FIFO: 512 depth, 128-bit | 16 | false | false | false | 16 | 16 | 1_(Normal) | 512 | inst/M00_AXIS_ACLK=675 inst/S00_AXIS_ACLK=675 | *ACLK | 675 | 72 | 220 | 0 | 2 | 1 | PRODUCTION 1.30 05-15-2022 | |||||||||||
xczu19eg | ffvb1517 | 2 | Data width converter: 32-bit to 128-bit | 16 | false | false | false | 16 | 4 | inst/M00_AXIS_ACLK=1289 inst/S00_AXIS_ACLK=1289 | *ACLK | 1288 | 25 | 195 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||||||||||
xczu19eg | ffvb1517 | 2 | Data width converter: 128-bit to 32-bit | 4 | false | false | false | 4 | 16 | inst/M00_AXIS_ACLK=1211 inst/S00_AXIS_ACLK=1211 | *ACLK | 1211 | 91 | 193 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||||||||||
xczu19eg | ffvb1517 | 2 | Data width converter: 128-bit to 512-bit | 64 | false | false | false | 64 | 16 | inst/M00_AXIS_ACLK=1058 inst/S00_AXIS_ACLK=1058 | *ACLK | 1058 | 23 | 736 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||||||||||
xczu19eg | ffvb1517 | 2 | Data width converter: 512-bit to 128-bit | 16 | false | false | false | 16 | 64 | inst/M00_AXIS_ACLK=1149 inst/S00_AXIS_ACLK=1149 | *ACLK | 1150 | 313 | 733 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||||||||||
xczu19eg | ffvb1517 | 2 | Register slice: 32-bit | 4 | false | false | false | 4 | 1 | 4 | inst/M00_AXIS_ACLK=1311 inst/S00_AXIS_ACLK=1311 | *ACLK | 1310 | 44 | 83 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||||
xczu19eg | ffvb1517 | 2 | Register slice: 128-bit | 16 | false | false | false | 16 | 1 | 16 | inst/M00_AXIS_ACLK=1140 inst/S00_AXIS_ACLK=1140 | *ACLK | 1140 | 144 | 299 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||||
xczu19eg | ffvb1517 | 2 | Register slice: 512-bit | 64 | false | false | false | 64 | 1 | 64 | inst/M00_AXIS_ACLK=1047 inst/S00_AXIS_ACLK=1047 | *ACLK | 1047 | 588 | 1164 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||||
xczu19eg | ffvb1517 | 2 | Switch: 1x2, 128-bit | 1 | 2 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=960 inst/M01_AXIS_ACLK=960 inst/S00_AXIS_ACLK=960 | *ACLK | 960 | 168 | 310 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||
xczu19eg | ffvb1517 | 2 | Switch: 1x4, 32-bit | 1 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=1003 inst/M01_AXIS_ACLK=1003 inst/M02_AXIS_ACLK=1003 inst/M03_AXIS_ACLK=1003 inst/S00_AXIS_ACLK=1003 | *ACLK | 1003 | 69 | 101 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||
xczu19eg | ffvb1517 | 2 | Switch: 1x4, 128-bit | 1 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=905 inst/M01_AXIS_ACLK=905 inst/M02_AXIS_ACLK=905 inst/M03_AXIS_ACLK=905 inst/S00_AXIS_ACLK=905 | *ACLK | 905 | 171 | 316 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||
xczu19eg | ffvb1517 | 2 | Switch: 1x4, 512-bit | 1 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=785 inst/M01_AXIS_ACLK=785 inst/M02_AXIS_ACLK=785 inst/M03_AXIS_ACLK=785 inst/S00_AXIS_ACLK=785 | *ACLK | 785 | 610 | 1181 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||
xczu19eg | ffvb1517 | 2 | Switch: 2x1, 128-bit | 2 | 1 | 16 | false | false | false | 16 | 16 | 16 | inst/M00_AXIS_ACLK=943 inst/S00_AXIS_ACLK=943 inst/S01_AXIS_ACLK=943 | *ACLK | 943 | 417 | 626 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||||
xczu19eg | ffvb1517 | 2 | Switch: 2x2, 128-bit | 2 | 2 | 16 | false | false | false | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=785 inst/M01_AXIS_ACLK=785 inst/S00_AXIS_ACLK=785 inst/S01_AXIS_ACLK=785 | *ACLK | 785 | 499 | 641 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||||||
xczu19eg | ffvb1517 | 2 | Switch: 4x1, 32-bit | 4 | 1 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=872 inst/S00_AXIS_ACLK=872 inst/S01_AXIS_ACLK=872 inst/S02_AXIS_ACLK=872 inst/S03_AXIS_ACLK=872 | *ACLK | 872 | 320 | 390 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||
xczu19eg | ffvb1517 | 2 | Switch: 4x1, 128-bit | 4 | 1 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=811 inst/S00_AXIS_ACLK=811 inst/S01_AXIS_ACLK=811 inst/S02_AXIS_ACLK=811 inst/S03_AXIS_ACLK=811 | *ACLK | 811 | 990 | 1254 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||
xczu19eg | ffvb1517 | 2 | Switch: 4x1, 512-bit | 4 | 1 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=680 inst/S00_AXIS_ACLK=680 inst/S01_AXIS_ACLK=680 inst/S02_AXIS_ACLK=680 inst/S03_AXIS_ACLK=680 | *ACLK | 680 | 3009 | 4716 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | ||||||||
xczu19eg | ffvb1517 | 2 | Switch: 4x4, 32-bit | 4 | 4 | 4 | false | false | false | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 | inst/M00_AXIS_ACLK=779 inst/M01_AXIS_ACLK=779 inst/M02_AXIS_ACLK=779 inst/M03_AXIS_ACLK=779 inst/S00_AXIS_ACLK=779 inst/S01_AXIS_ACLK=779 inst/S02_AXIS_ACLK=779 inst/S03_AXIS_ACLK=779 | *ACLK | 779 | 577 | 497 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||
xczu19eg | ffvb1517 | 2 | Switch: 4x4, 128-bit | 4 | 4 | 16 | false | false | false | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | inst/M00_AXIS_ACLK=713 inst/M01_AXIS_ACLK=713 inst/M02_AXIS_ACLK=713 inst/M03_AXIS_ACLK=713 inst/S00_AXIS_ACLK=713 inst/S01_AXIS_ACLK=713 inst/S02_AXIS_ACLK=713 inst/S03_AXIS_ACLK=713 | *ACLK | 713 | 1429 | 1361 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 | |||||
xczu19eg | ffvb1517 | 2 | Switch: 4x4, 512-bit | 4 | 4 | 64 | false | false | false | 64 | 64 | 64 | 64 | 64 | 64 | 64 | 64 | inst/M00_AXIS_ACLK=653 inst/M01_AXIS_ACLK=653 inst/M02_AXIS_ACLK=653 inst/M03_AXIS_ACLK=653 inst/S00_AXIS_ACLK=653 inst/S01_AXIS_ACLK=653 inst/S02_AXIS_ACLK=653 inst/S03_AXIS_ACLK=653 | *ACLK | 653 | 7208 | 4821 | 0 | 0 | 0 | PRODUCTION 1.30 05-15-2022 |
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