Performance and Resource Utilization for DFX AXI Shutdown Manager v1.0

Vivado Design Suite Release 2023.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 599 911 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 407 589 911 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 415 545 893 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 454 550 894 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 610 921 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 612 920 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 399 545 903 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 423 552 902 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 663 1131 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 438 679 1131 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 368 589 1114 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 454 629 1113 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 423 682 1142 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 415 676 1140 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 399 612 1122 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 1 xc7k325tfbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 399 612 1123 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 508 625 915 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 524 623 917 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 532 571 897 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 508 565 896 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 516 622 923 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 493 606 922 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 532 577 907 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 508 579 907 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 500 666 1135 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 508 679 1134 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 524 619 1118 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 540 617 1117 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 508 676 1142 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 524 697 1146 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 493 613 1126 0 0 0 PRODUCTION 1.25 12-04-2018
xcku040 fbva676 1 xcku040-fbva676-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 508 627 1127 0 0 0 PRODUCTION 1.25 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 774 617 914 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 681 602 913 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 790 574 899 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 750 570 895 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 782 620 924 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 735 627 922 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 806 585 912 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 821 583 907 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 727 667 1133 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 758 670 1133 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 620 1116 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 727 608 1115 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 743 675 1142 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 750 694 1142 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 766 614 1124 0 0 0 PRODUCTION 1.29 05-01-2022
xcku13p ffve900 1 xcku13p-ffve900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 782 628 1129 0 0 0 PRODUCTION 1.29 05-01-2022

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 415 586 911 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 446 607 913 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 438 548 894 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 368 527 894 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 423 603 920 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 438 621 923 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 438 557 903 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 560 902 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 407 659 1131 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 423 678 1131 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 617 1114 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 431 618 1118 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 399 679 1140 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 415 683 1140 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 423 614 1122 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 1 xc7vx690tffg1157-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 415 620 1122 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 500 609 913 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 500 614 915 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 516 569 895 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 524 571 897 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 500 618 923 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 508 641 922 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 500 578 906 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 532 579 907 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 462 622 1133 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 493 659 1138 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 532 625 1117 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 493 606 1117 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 477 634 1143 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 485 641 1142 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 493 601 1125 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffvc1517 1 xcvu095-ffvc1517-1-i_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 477 585 1126 0 0 0 PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 790 624 914 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 743 614 913 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 798 571 895 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 782 569 895 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 758 618 922 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 735 615 922 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 743 574 904 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 790 578 904 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 758 670 1133 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 743 679 1133 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 829 620 1115 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 813 628 1116 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 712 666 1142 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 766 692 1142 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 743 617 1124 0 0 0 PRODUCTION 1.28 03-30-2022
xcvu11p flga2577 1 xcvu11p-flga2577-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 630 1124 0 0 0 PRODUCTION 1.28 03-30-2022

Zynq-7000

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 591 913 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 399 591 911 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 407 541 893 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 544 893 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 431 598 920 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 399 596 920 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 431 552 902 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 446 559 903 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 438 673 1131 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 438 691 1132 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 462 619 1113 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 438 614 1113 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 415 670 1140 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 438 702 1141 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 446 624 1123 0 0 0 PRODUCTION 1.12 2019-11-22
xc7z045 fbg676 1 xc7z045fbg676-1_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 423 608 1122 0 0 0 PRODUCTION 1.12 2019-11-22

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
RESET_ACTIVE_LEVEL
RP_IS_MASTER
CTRL_INTERFACE_TYPE
CTRL_ADDR_WIDTH
DP_PROTOCOL
DP_AXI_ADDR_WIDTH
DP_AXI_DATA_WIDTH
DP_AXI_ID_WIDTH
DP_AXI_AWUSER_WIDTH
DP_AXI_WUSER_WIDTH
DP_AXI_BUSER_WIDTH
DP_AXI_ARUSER_WIDTH
DP_AXI_RUSER_WIDTH
DP_AXI_RESP
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 790 608 913 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 798 623 914 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 798 571 896 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 782 571 895 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 758 617 922 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 0 clk 790 638 922 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 681 555 904 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4LITE_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4LITE 32 32 0 0 0 0 0 0 3 clk 813 584 911 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 735 670 1133 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_0_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 766 681 1133 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_false 0 false 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 766 620 1118 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_0_resp_3_rp_is_master_true 0 true 0 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 813 620 1115 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 743 679 1142 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_0_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 0 clk 758 693 1142 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_false 0 false 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 774 627 1124 0 0 0 PRODUCTION 1.30 05-15-2022
xczu4cg fbvb900 1 xczu4cg-fbvb900-1-e_dp_protocol_AXI4MM_ctrl_1_resp_3_rp_is_master_true 0 true 1 32 AXI4MM 32 32 0 0 0 0 0 0 3 clk 766 626 1125 0 0 0 PRODUCTION 1.30 05-15-2022

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