Versal ACAP Register Reference > Module Summary > CPM5_SLCR Module > NPI_GT_QD3_IR_STATUS (CPM5_SLCR) Register

NPI_GT_QD3_IR_STATUS (CPM5_SLCR) Register

NPI_GT_QD3_IR_STATUS (CPM5_SLCR) Register Description

Register NameNPI_GT_QD3_IR_STATUS
Relative Address0x00000004EC
Absolute Address 0x00FCDD04EC (CPM5_SLCR)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status Register for NPI GT Quad 3. This is a sticky register that holds the value of the error until cleared by a value of 1.

NPI_GT_QD3_IR_STATUS (CPM5_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
int3 3wtcReadable, write a 1 to clear0x0Status for NPI int3 error.
int2 2wtcReadable, write a 1 to clear0x0Status for NPI int2 error.
int1 1wtcReadable, write a 1 to clear0x0Status for NPI int1 error.
int0 0wtcReadable, write a 1 to clear0x0Status for NPI int0 error.