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Zynq DPU v3.1 IP Product Guide
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Zynq DPU v3.1 IP Product Guide
Development Flow
Customizing and Generating the Core in MPSoC
Generate Bitstream
Zynq DPU v3.1 IP Product Guide
Introduction
Overview
Product Specification
DPU Configuration
Clocking and Resets
Development Flow
Customizing and Generating the Core in MPSoC
Add DPU IP into Repository or Upgrade DPU from a Previous Version
Add DPU IP into Block Design
Configure DPU Parameters
Connecting a DPU with a Processing System in the Xilinx SoC
Assign Register Address for DPU
Generate Bitstream
Generate BOOT.BIN
Device Tree
Customizing and Generating the Core in Zynq-7000 Devices
Cutomizing and Generating the Core in Vitis Integrated Design Environment (IDE)
Example Design
Generate Bitstream
Click
Generate Bitstream
in
Vivado
as shown below.
Figure
1
:
Generate Bitstream