reg_dpu_reset
The reg_dpu_reset register controls the resets of all DPU cores integrated in the DPU IP. The lower three bits of this register control the reset of up to three DPU cores. All the reset signals are active-High. The details of reg_dpu_reset are shown in the following table.
| Register | Address Offset | Width | Type | Description |
|---|---|---|---|---|
| reg_dpu_reset | 0x004 | 32 | R/W | [n] – DPU core n reset |