reg_dpu_isr
The reg_dpu_isr register represents the interrupt status of all cores in the DPU IP. The lower three bits of this register shows the interrupt status of up to three DPU cores. The details of reg_dpu_irq are shown in the following table.
| Register | Address Offset | Width | Type | Description |
|---|---|---|---|---|
| reg_dpu_isr | 0x608 | 32 | R | [n] – DPU core n interrupt status |