Vivado TRD Overview

The TRD creates an image classification application running a popular deep neural network model, Resnet50, on a Xilinx® Zynq® UltraScale+™ MPSoC. The overall functionality of the TRD is partitioned between the processing system (PS) and programmable logic (PL), where the DPU resides for optimal performance.

The following figure shows the TRD block diagram. The host communicates with the ZCU102 board through an Ethernet or UART port. The input images for the TRD are stored in an SD card. When the TRD is running, the input data is loaded into DDR memory, then the DPU reads the data from DDR memory and writes the results back to DDR memory. Results are shown on the host screen from the APU through Ethernet or UART.