3GPP LTE PUCCH Receiver 製品およびソフトウェア要件

Hardware Evaluation Time Out Period * : ~ 2-3 hrs


LogiCORE™ バージョン AXI サポート ソフトウェア サポート サポートするデバイス ファミリ
3GPP LTE PUCCH Receiver v2.0 AXI4-Stream Vivado® 2020.2 Versal™ ACAP
UltraScale+™ ファミリ
Kintex® UltraScale™
Virtex® UltraScale
Kintex-7 / -2L
Virtex-7 / -2L
3GPP LTE PUCCH Receiver v1.0 AXI4-Stream ISE® 13.4 Kintex-7 / -2L
Virtex-7 / -2L
Virtex-6 LXT / SXT / CXT / -1L
Virtex-5 FXT / SXT / LXT

Download the required software from the Xilinx.com Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.

* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.