General Description: Why do the Block RAM outputs display "X's" on the output in functional simulation?
The VHDL UNISIMS library uses the VITAL constructs to pass a default timing delay value to the models; during functional simulation, this warns you about timing violations that will appear in back-annotated simulation. This default timing delay value is 0.01ns (10ps).
If the simulation is run at a 1ns time step, then these values are ignored. However, when the simulation is run with a 1ps time step, these delay values come into effect. Xilinx recommends running functional simulations using the 1ps time step so that you are warned about timing violations early in the design stage (during functional simulation). Otherwise, design modifications might be needed later in the design cycle to get around these timing issues.
For Block RAMs, several default timing delays are built into the simulation model. Whenever a violation triggers, the output for that clock cycle may be unknown. In order to see if a violation is indeed being shown, the variable "violation" can be added to the waveform window. Whenever the "violation" variable has a non-zero value, a violation is being reported.
Timing checks can be disabled in functional simulation by setting a switch in the simulator. In MTI, timing checks can be disabled by using the "+notimingchecks" switch in the vsim command line.