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AR# 10134

System Generator for DSP - Is it possible to pass user-defined constraints into the generated VHDL?

説明

General Description: 

Is it possible to pass user-defined constraints into the generated VHDL?

ソリューション

No -- there is no current mechanism for passing user-defined constraints into the generated VHDL.

AR# 10134
日付 05/14/2014
ステータス アーカイブ
種類 一般
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