AR# 10294: 1.0 System Generator for DSP - Interpolated FIR filter (IFIR) will not work in hardware when created with System Generator
1.0 System Generator for DSP - Interpolated FIR filter (IFIR) will not work in hardware when created with System Generator
Keywords: SysGen, zero packing factor, COE, coefficients, taps
General Description: Using System Generator v1.0, the Interpolated FIR (IFIR) will not work in hardware created using the System Generator "Generate" token.
There is a discrepancy between how the coefficients are specified for the Interpolated FIR Coefficients in the System Generator Block Parameters and CORE Generator.
The System Generator GUI is missing the zero-packing factor "k"; when you specify the coefficients, they would look something like [1 0 0 2 0 0 1].
In the CORE Generator GUI, you would use a coefficient file "COE [1 2 1]", then set k=3.
To work around this issue, follow these steps:
1. Use the Xilinx Blockset Interpolate FIR (as noted above) for the Simulink simulation. In the block parameters, use the coefficients with the zeros included [1 0 0 2 0 0 1]. Run the Simulink simulation. Once you are satisfied with the simulation, run the System Generator "Generate" token when appropriate.
2. Create a file with the .coe extension that contains the following:
3. Before implementing the design, you must regenerate the IFIR core by running CORE Generator in stand-alone mode. After CORE Generator comes up and you choose the project, go to:
Digital Signal Processing -> Filters -> Finite Impulse Response (FIR)
4. Double-click on the Distributed Arithmetic FIR filter. When the window comes up, type in the component name that matches the component name in the Simulink model. Choose "Interpolated." Choose a zero packing factor of 3.
5. Click on the "Coefficients" button, then load the coefficients file from Step 2.
6. Choose any other appropriate options.
7. Click the "Generate" button.
8. If you have not already done so, you may run synthesis on the VHDL created by the System Generator. You can use "VHDLFiles" file for the order and location of all VHDL files.
8. Using all other files created in Simulink, you can now implement the design in the Xilinx tools.
NOTE: The VHDL functional simulation will not be correct. To use the new configuration parameters, you must use the .vho file that was created when you ran CORE Generator in stand-alone mode, and update the VHDL "wrapper" file for the IFIR block.