説明

General Description:

What slew rates can be expected on 9500XL outputs as the capacitive

load increases?

ソリューション

Note: The numbers indicated below are based upon a single

data point and are given solely as a service for our

customers to estimate the effects of additional

capacitive loading. Xilinx does not guarantee these

numbers.

Test conditions:

Temp. Ambient = 25C

VCCio = 3.3V

VCCint = 3.3V

Rise and Fall times are equal to the time difference where the output

is 10% and 90% of VCCIO.

Slow Slew Rate - Low to High :

LOAD RISE TIME

0pF 1.5ns

10pF 2.1ns

47pF 5.5ns

100pF 8.0ns

Fast Slew Rate - Low to High :

LOAD RISE TIME

0pF 0.8ns

10pF 1.4ns

47pF 3.7ns

100pF 6.5ns

Slow Slew Rate - High to Low :

LOAD FALL TIME

0pF 1.3ns

10pF 1.8ns

47pF 4.5ns

100pF 6.2ns

Fast Slew Rate - High to Low :

LOAD FALL TIME

0pF 0.8ns

10pF 1.4ns

47pF 3.5ns

100pF 5.5ns