AR# 10461: 6.1i CORE Generator - Behavioral models for Verilog simulation might give cores race conditions
6.1i CORE Generator - Behavioral models for Verilog simulation might give cores race conditions
When I run a Verilog behavioral simulation for certain Xilinx CORE Generator cores, the cores are given race conditions. (Most XilinxCoreLib models do not display race conditions when they are simulated with ModelSim (MTI) simulator. However, they may display different behavior when simulated with other Verilog simulators such as VCS, Verilog-XL, and NC-Verilog.)
Affected cores are:
- Adder Subtracter
- Asynchronous FIFO
- Bit Gate
- DA FIR Filter
- Distributed Memory
- Dynamic Constant Coefficient Multiplier
- FD Based Register
- Variable Parallel Multiplier
- Single and Dual Port Block Memory
Each Verilog simulator handles race conditions differently, and not all simulators are known to flag race conditions. The Xilinx Core development group does not have access to all Verilog simulators; however, the following information is known:
- Synopsys VCS simulator: Can detect race conditions. See the VCS documentation on how to enable a race detection tool.
- Cadence Verilog-XL and NC-Verilog: Can detect race conditions, but each simulator has its own scheduling engine; therefore, the outputs might vary.
- ModelSim SE/EE Plus: We are awaiting a response from Model Technology support.
Most of the cores developed after 5.1i IP update #1 have been tested for race conditions. However, the cores prior to that have not been. For those cores with race conditions, please use the latest core, or we suggest that you work around race conditions by running post-NGDBuild simulation rather than behavioral simulation.