AR# 10573


3.1i XST - VERILOG synthesis: XST hangs at 50% when synthesizing a Verilog file.


Keywords: hang, Verilog, CPLD

Urgency: Standard

General Description:
XST has been seen to hang at 50% when synthesizing for CPLDs.


This problem is fixed in the latest 3.1i Service Pack available at: The first
service pack containing the fix is 3.1i Service Pack 6.
AR# 10573
日付 08/19/2002
ステータス アーカイブ
種類 一般
People Also Viewed