UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10573

3.1i XST - VERILOG synthesis: XST hangs at 50% when synthesizing a Verilog file.

説明

Keywords: hang, Verilog, CPLD

Urgency: Standard

General Description:
XST has been seen to hang at 50% when synthesizing for CPLDs.

ソリューション

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 6.
AR# 10573
日付 08/19/2002
ステータス アーカイブ
種類 一般
このページをブックマークに追加