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  3. AR# 1061: SYNPLIFY: How is the top level module or entity/architecture determined?
  4. AR# 10612: 4.2i Foundation - How do I translate symbol and pin names during EDIF2NGD and avoid the default usage of Xilinx primitives?

AR# 10612

4.2i Foundation - How do I translate symbol and pin names during EDIF2NGD and avoid the default usage of Xilinx primitives?

説明

Keywords: translate, symbol, pin, names, EDIF2NGD, RAM32X1, ttl

Urgency: Standard

General Description:
Is it possible to translate symbol and pin names during EDIF2NGD and instruct the software to not use Xilinx primitives (such as the RAM32X1S)?

ソリューション

The software contains a hidden feature that allows you to translate symbol and pin names during EDIF2NGD. The feature is a "translation table," and it uses a text file with a .ttl extension.

For an example, see $XILINX/virtexe/data/virtexe.ttl: The first entry translates CLKDLLs to CLKDLLEs. This feature can be used to translate the RAM32x1S to a non-primitive name -- a macro file will then be available for that new name.

For example:

The following lines in the virtexe.ttl translate the RAM32X1S to a AMRAM32X1S:

RAM32X1S = AMRAM32X1S {
D;
WE;
A0;
A1;
A2;
A3;
A4;
WCLK;
O;
};

The software does not search for the RAM32X1S primitive. Instead, it searches for the AMRAM32X1S netlist in the project directory.
AR# 10612
日付 08/11/2003
ステータス アーカイブ
種類 一般