AR# 10642


3.3i Foundation ISE Project Importer - Schematics containing similar bus and pin names cause synthesis errors


Keywords: ISE, Project Navigator, Project Importer

Urgency: Standard

General Description:
If a bus pin on a schematic symbol and a single net pin on the same
symbol have the same root name, a problem occurs when the VHDL
netlist is generated from the schematic, and synthesis will fail.

Example: A symbol with bus pin "c[7:0]" and clock pin is simply named
"c." This works successfully through schematic flow, but the VHDL
netlist will cause an error.


The signal pin or bus pin must be renamed. This can be done in
the schematic, or in the resulting VHDL structural netlist
AR# 10642
日付 10/21/2002
ステータス アーカイブ
種類 一般
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