UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10699

3.1i CORE Generator - Variable Parallel Multiplier Error:The core cannot be generated when input is '4' in Input Data Width(A) and '2' (B).

説明

Keywords: CORE Generator, variable parallel multiplier, muliply generator

Urgency: Standard

General Description:
When generating a CORE Generator Variable Parallel Multiplier v2_0 with Input
Data Width(A) = 4 and Input Data Width(B) = 2, I encounter the following error
message:

ERROR: Elaboration of core Variable_Parallel_Multiplier failed.
ERROR: Customization parameter rule checks failed. Terminating core
elaboration: 2-bit multiplier (Data Width B=2) cannot have pipelined
registers only output registers
ERROR: SimGenerator: Failure to set Sim customization parameters for
core Variable_Parallel_Multiplier
ERROR: Elaboration of core Variable_parallel_Multiplier failed.

ソリューション

This is a GUI problem that involves accepting certain combinations of input width.

Variable Parallel Multiplier v2_0 is being replaced by Multiply Generator v2_0 (Multiplier
v2_0), which was released with CORE Generator IP Update #2. If a problem occurs while
generating Variable Parallel Multiplier, use Multiply Generator instead.
AR# 10699
日付 08/23/2002
ステータス アーカイブ
種類 一般
このページをブックマークに追加